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PDF X96010 Data sheet ( Hoja de datos )
| Número de pieza | X96010 | |
| Descripción | Sensor Conditioner | |
| Fabricantes | Intersil Corporation | |
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Data Sheet
October 25, 2005
X96010
FN8214.1
Sensor Conditioner with Dual Look Up
Table Memory and DACs
FEATURES
• Two Programmable Current Generators
—±3.2 mA max.
—8-bit (256 Step) Resolution
—External Resistor Pins to Set Full Scale Cur-
rent Output
• External Sensor Input (Single Ended)
• Integrated 8-bit A/D Converter
• Internal Voltage Reference with Output/Input
• Temperature Compensation
• EEPROM Look-up Tables
• Hot Pluggable
• Write Protection Circuitry
—Intersil BlockLock™
—Logic Controlled Protection
• 2-wire Bus with 3 Slave Address Bits
• 3V to 5.5V, Single Supply Operation
• Package
—14 Ld TSSOP
• Pb-Free Plus Anneal Available (RoHS Compliant)
APPLICATIONS
• PIN Diode Bias Control
• RF PA Bias Control
• Temperature Compensated Process Control
• Laser Diode Bias Control
• Fan Control
• Motor Control
• Sensor Signal Conditioning
• Data Aquisition Applications
• Gain vs. Temperature Control
• High Power Audio
• Open Loop Temperature Compensation
• Close Loop Current, Voltage, Pressure, Temper-
ature, Speed, Position Programmable Voltage
sources, electronic loads, output amplifiers, or
function generator
DESCRIPTION
The X96010 is a highly integrated bias controller which
incorporates two digitally controlled Programmable Cur-
rent Generators and temperature compensation with
dedicated look-up tables. All functions of the device are
controlled via a 2-wire digital serial interface.
Two temperature compensated Programmable Cur-
rent Generators, vary the output current with tempera-
ture according to the contents of the associated
nonvolatile look-up table. The look-up table may be
programmed with arbitrary data by the user via the 2-
wire serial port, and an external temperature sensor
may be used to control the output current response.
Ordering Information
PART NUMBER
PART
TEMP
MARKING RANGE (°C)
PACKAGE
X96010V14I
X96010V I
-40 to 100 14 Ld TSSOP
X96010V14IZ
(Note)
X96010VI Z
-40 to 100 14 Ld TSSOP
(Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
PIN CONFIGURATION
A0
A1
A2
Vcc
WP
SCL
SDA
1
2
3
4
5
6
7
14 I2
13 VRef
12 VSense
11 Vss
10 R2
9 R1
8 I1
TSSOP 14L
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
X96010
D/A CONVERTER CHARACTERISTICS (See pg. 4 for Standard Conditions)
Symbol
IFS
OffsetDAC
FSErrorDAC
DNLDAC
INLDAC
VISink
VISource
IOVER
IUNDER
trDAC
TCOIout
Parameter
I1 or I2 full scale current
I1 or I2 D/A converter offset error
I1 or I2 D/A converter full scale error
I1 or I2 D/A converter
Differential Nonlinearity
I1 or I2 D/A converter Integral Nonlin-
earity with respect to a straight line
through 0 and the full scale value
I1 or I2 Sink Voltage Compliance
I1 or I2 Source Voltage Compliance
I1 or I2 overshoot on D/A Converter
data byte transition
I1 or I2 undershoot on D/A Converter
data byte transition
I1 or I2 rise time on D/A Converter data
byte transition; 10% to 90%
Temperataure coefficient of output
current due to internal parameters
Min
1.56
1
-2
-0.5
-1
1.2
2.5
0
0
5
-100
Typ Max Unit Test Conditions / Notes
1.58 1.6 mA See note 1, 5, R = 510Ω
3.2 mA See note 1, 4, 6, R = 255Ω
1 LSB See notes 2 and 3.
2 LSB
0.5 LSB
1 LSB
Vcc V See note 5
Vcc V See note 4, 6
Vcc-1.2 V See note 5
Vcc-2.5 V See note 4, 6
0 µA DAC input byte changing from
00h to FFh and vice
0
µA
versa, V(I1) and V(I2) are
Vcc - 1.2V in source mode
and 1.2V in sink mode.
30 µs See note 4.
+100 ppm/ See Figure 7.
°C VRMbit = “0”
Notes: 1. DAC input Byte = FFh, Source or sink mode.
[ ]2. LSB is defined as
2
3
x
V(VRef)
255
divided by the resistance between R1 or R2 to Vss.
3. OffsetDAC: The Offset of a DAC is defined as the deviation between the measured and ideal output, when the DAC input is 01h. It is
expressed in LSB.
FSErrorDAC: The Full Scale Error of a DAC is defined as the deviation between the measured and ideal output, when the input is FFh. It
is expressed in LSB. The OffsetDAC is subtracted from the measured value before calculating FSErrorDAC.
DNLDAC: The Differential Non-Linearity of a DAC is defined as the deviation between the measured and ideal incremental change in
the output of the DAC, when the input changes by one code step. It is expressed in LSB. The measured values are adjusted for Offset
and Full Scale Error before calculating DNLDAC.
INLDAC: The Integral Non-Linearity of a DAC is defined as the deviation between the measured and ideal transfer curves, after adjust-
ing the measured transfer curve for Offset and Full Scale Error. It is expressed in LSB.
4. These parameters are periodically sampled and not 100% tested.
5. V(I1) and V(I2) are VCC - 1.2V in source mode and 1.2V in sink mode. In this range the current at I1 or I2 varies <1%.
6. The maximum current, sink or source, can be set with an external resistor to 3.2 mA with a minimum VCC = 4.5V. The compliance volt-
age changes to 2.5V from the sourcing rail, and the current variation is <1%.
5 FN8214.1
October 25, 2005
5 Page 
Figure 4. Control and Status Register Format
X96010
Byte
Address
MSB
7 6 5 4 3 21
80h
Non-Volatile
I2DS
I1DS
I1 and I2 Direction
0: Source
1: Sink
NV1234 ADCfiltOff
Control
1, 2, 3, 4
Volatility
0: Volatile
1: Non-
volatile
ADC
filtering
0: On
1: Off
1
VRM
Voltage
Reference
Mode
0: Internal
1: External
0
81h
Volatile or
Non-Volatile
Direct Access to LUT1
Reserved Reserved
L1DA5
L1DA4
L1DA3
L1DA2
L1DA1
82h
Volatile or
Non-Volatile
Direct Access to LUT2
Reserved Reserved
L2DA5
L2DA4
L2DA3
L2DA2
L2DA1
83h
Volatile or
Non-Volatile
Direct Access to DAC1
D1DA7 D1DA6
D1DA5
D1DA4
84h
Volatile or
Non-Volatile
Direct Access to DAC2
D2DA7 D2DA6
D2DA5
D2DA4
D1DA3
D2DA3
D1DA2
D2DA2
D1DA1
D2DA1
LSB
0
0
L1DA0
L2DA0
D1DA0
D2DA0
Register
Name
Control 0
Control 1
Control 2
Control 3
Control 4
85h
Non-Volatile D2DAS
L2DAS
D1DAS L1DAS
0
0
0
0 Control 5
Direct
Access
to DAC2
0: Disabled
1: Enabled
Direct
Access
to LUT2
0: Disabled
1: Enabled
Direct
Access
to DAC1
0: Disabled
1: Enabled
Direct
Access
to LUT1
0: Disabled
1: Enabled
86h
Volatile
WEL Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Write
Enable
Latch
0: Write
Disabled
1: Write
Enabled
ADC Output
87h
Volatile
AD7
AD6 AD5 AD4
AD3
AD2
AD1
AD0
Control 6
Status
Registers in byte addresses 88h through 8Fh are reserved.
Register bits shown as 0 or 1 should always use those values for proper operation.
11 FN8214.1
October 25, 2005
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet X96010.PDF ] | |
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