|
|
PDF U630H64 Data sheet ( Hoja de datos )
| Número de pieza | U630H64 | |
| Descripción | HardStore 8K x 8 nvSRAM | |
| Fabricantes | Simtek | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de U630H64 (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
U630H64
HardStore 8K x 8 nvSRAM
Features
Description
S High-performance CMOS nonvola-
tile static RAM 8192 x 8 bits
S 25, 35 and 45 ns Access Times
S 12, 20 and 25 ns Output Enable
Access Times
S Hardware STORE Initiation
(STORE Cycle Time < 10 ms)
S Automatic STORE Timing
S 105 STORE cycles to EEPROM
S 10 years data retention in
EEPROM
S Automatic RECALL on Power Up
S Hardware RECALL Initiation
(RECALL Cycle Time < 20 µs)
S Unlimited RECALL cycles from
EEPROM
S Unlimited Read and Write to SRAM
S Single 5 V ± 10 % Operation
S Operating temperature ranges:
0 to 70 °C
-40 to 85 °C
S QS 9000 Quality Standard
S ESD characterization according
MIL STD 883C M3015.7-HBM
(classification see IC Code
Numbers)
S RoHS compliance and Pb- free
S Packages: PDIP28 (300 mil)
SOP28 (330 mil)
The U630H64 has two separate
modes of operation: SRAM mode
and nonvolatile mode, determined
by the state of the NE pin.
In SRAM mode, the memory ope-
rates as an ordinary static RAM. In
nonvolatile operation, data is
transferred in parallel from SRAM
to EEPROM or from EEPROM to
SRAM. In this mode SRAM
functions are disabled.
The U630H64 is a fast static RAM
(25, 35, 45 ns), with a nonvolatile
electrically erasable PROM
(EEPROM) element incorporated
in each static memory cell. The
SRAM can be read and written an
unlimited number of times, while
independent nonvolatile data resi-
des in EEPROM. Data transfers
from the SRAM to the EEPROM
(the STORE operation), or from
the
EEPROM to the SRAM (the
RECALL operation) are initiated
through the state of the NE pin.
The U630H64 combines the high
performance and ease of use of a
fast SRAM with nonvolatile data
integrity.
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvola-
tile information is transferred into
the SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
Pin Configuration
Pin Description
NE
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1 28
2 27
3 26
4 25
5 24
6 23
7 PDIP 22
8 SOP 21
9 20
10 19
11 18
12 17
13 16
14 15
Top View
VCC
W
n.c.
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
April 7, 2005
Signal Name
A0 - A12
DQ0 - DQ7
E
G
W
NE
VCC
VSS
Signal Description
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Nonvolatile Enable
Power Supply Voltage
Ground
1
1 page  
Read Cycle 1: Ai-controlled (during Read cycle: E = G = VIL, W = NE = VIH)f
Ai
DQi
Output
tcR (1)
Address Valid
ta(A) (2)
Previous Data Valid
tv(A) (9)
Output Data Valid
Read Cycle 2: G-, E-controlled (during Read cycle: W = NE = VIH)g
Ai
E
G
DQi
Output
ICC
tcR (1)
Address Valid
ta(A) (2)
ta(E) (3)
ten(E) (7)
ta(G) (4)
ten(G) (8)
High Impedance
ACTIVE
tPU 10
STANDBY
tdis(E) (5)
tdis(G) (6)
Output Data Valid
tPD (11)
U630H64
No.
Switching Characteristics
Write Cycle
12 Write Cycle Time
13 Write Pulse Width
14 Write Pulse Width Setup Time
15 Address Setup Time
16 Address Valid to End of Write
17 Chip Enable Setup Time
18 Chip Enable to End of Write
19 Data Setup Time to End of Write
20 Data Hold Time after End of Write
21 Address Hold after End of Write
22 W LOW to Output in High-Zh, i
23 W HIGH to Output in Low-Z
Symbol
25 35 45
Unit
Alt. #1 Alt. #2 IEC Min. Max. Min. Max. Min. Max.
tAVAV
tAVAV
tcW 25
35
45
tWLWH
tw(W) 20 30 35
tWLEH tsu(W) 20 30 35
tAVWL
tAVEL
tsu(A)
0
0
0
tAVWH tAVEH tsu(A-WH) 20 30 35
tELWH
tsu(E) 20 30 35
tELEH
tw(E)
20
30
35
tDVWH tDVEH
tsu(D)
12
18
20
tWHDX tEHDX
th(D)
0
0
0
tWHAX tEHAX
th(A)
0
0
0
tWLQZ
tdis(W) 10 13 15
tWHQX
ten(W)
5
5
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
April 7, 2005
5
5 Page 
Test Configuration for Functional Check
U630H64
5V
VCCt
A0
A1
A2
A3 DQ0
A4 DQ1
480
VIH
A5
A6
DQ2
A7 DQ3
A8 DQ4
A9 DQ5
VIL
A10
A11
DQ6
A12 DQ7
VO
NE
E
W
G VSS
30 pF s
255
s: In measurement of tdis-times and ten-times the capacitance is 5 pF.
t: Between VCC and VSS must be connected a high frequency bypass capacitor 0.1 µF to avoid disturbances.
Capacitancee
Conditions
Symbol
Min.
Max.
Input Capacitance
Output Capacitance
VCC = 5.0 V
VI = VSS
f = 1 MHz
Ta = 25 °C
CI
CO
All pins not under test must be connected with ground by capacitors.
8
7
Unit
pF
pF
Ordering Code
Example
U630H64
S C 25 G1
Type
ESD Class
blank > 2000 V
B > 1000 V
Package
D = PDIP28 (300 mil)
S = SOP28 (330 mil) Type 1
S2 = SOP28 (330 mil) Type 2
u: on special request
Operating Temperature Range
C = 0 to 70 °C
K = -40 to 85 °C
Leadfree Option
blank = Standard Package
G1 = Leadfree Green Package u
Access Time
25 = 25 ns
35 = 35 ns u
45 = 45 ns u
Device Marking (example)
Product specification
Internal Code
ZMD
U630H64SC
25 Z 0425
G1
Date of manufacture
(The first 2 digits indicating
the year, and the last 2
digits the calendar week.)
Leadfree Green Package
April 7, 2005
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet U630H64.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| U630H64 | HardStore 8K x 8 nvSRAM | Simtek |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |