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PDF UW2453 Data sheet ( Hoja de datos )
| Número de pieza | UW2453 | |
| Descripción | Single Chip Transceiver | |
| Fabricantes | Bubec | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de UW2453 (archivo pdf) en la parte inferior de esta página. Total 24 Páginas | ||
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www.DataSheet4U.com
Revised Date: March 18, 2005
Product # : UW2453
UW2453/2453L
Data Sheet
(Preliminary)
Doc. #: DS-2453-01
<Rev. 0.0>
The content of this technical information is subject to change without notice.
Please contact UBEC for further information.
All rights strictly reserved. Any portion of this paper shall not be reproduced, copied, or transformed to any
other forms without permission from Uniband electronics corp. .
Uniband Electronics Corp. (Taiwan)
3F-2, No. 192, Dongguang Rd.
Hsinchu 300, Taiwan
TEL: +886-3-5729898
FAX: +886-3-5718599
http:// www.ubec.com.tw
Uniband Electronics Corp. (U.S.A.)
826, North Hillview Drive, Milpitas.
CA 95035, USA
TEL: +1-408-935-7888
FAX: +1-408-935-7889
Confidential
Doc. #: DS-2453-01 <Rev. 0.0>
Page 1/ 24
1 page  
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Product # : UW2453
Table 1.
Pin Descriptions
Pin type abbreviation: A = Analog, D = Digital, I = Input, O = Output
PIN SYMBOL
TYPE
DESCRIPTION
1 VDD_PA1
2 GND_PA
3 PA_OUT1
4 PA_OUT2
5 VDD_PA2
6 PA_DET
7 VDD_LNA
8 RFIN_P
9 RFIN_M
10 VDD_MXR
11 RXTX
12 PAON
13 VCO_TUNE
14 GND_VCO
15 VREG_OUT
16 VDD_LO
17 VDD_PLL
18 VDD_CP
19 GND_CP
20 LOCK/GS
21 DATA
22 EN
23 VDD_BUF
24 REF_CLK
25 GND_DIG
26 VDD_DIG
27 CLK
28 TX_IP
29 TX_IM
30 TX_QP
31 TX_QM
PA power supply. Bypass with a cap as close to the pin as possible.
PA ground
AO PA 1st stage open collector output.
AO PA 2nd stage open collector output. It is TX RF output.
PA power supply. Bypass with a cap as close to the pin as possible.
PA power detector output.
LNA power supply. Bypass with a cap as close to the pin as possible.
AI LNA differential RF input (+)
AI LNA differential RF input (-)
RX mixer power supply. Bypass with a cap as close to the pin as
possible.
DI RX and TX mode select
DI PA turn on/off control
PLL loop cap to ground
VCO ground
Regulated supply for VCO. Bypass with caps to ground
LO power supply. Bypass with a cap as close to the pin as possible.
PLL power supply. Bypass with a cap as close to the pin as possible.
Charge-pump supply. Bypass with a cap as close to the pin as possible.
Ground for charge pump circuit
DIO Synthesizer lock indicator or GS1~7 latch control
DI Three-wire bus data signal
DI Three-wire bus enable
Clock buffer supply. Bypass with a cap as close to the pin as possible.
AI Reference clock input
Ground for digital circuit
Digital circuit supply. Bypass with a cap as close to the pin as possible.
DI Three-wire bus clock
AI Transmitter I channel differential input (+)
AI Transmitter I channel differential input (-)
AI Transmitter Q channel differential input (+)
AI Transmitter Q channel differential input (-)
Confidential
Doc. #: DS-2453-01 <Rev. 0.0>
Page 5/ 24
5 Page 
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Product # : UW2453
GS1=0, GS2=0, VGA gain = 16 dB
21
Input IP2
(Including matching)
(Note 5)
GS1=1, GS2=1, VGA gain = 16 dB
GS1=1, GS2= 0, VGA gain = 16 dB
GS1=0, GS2=1, VGA gain = 16 dB
30
30
50
dBm
GS1=0, GS2=0, VGA gain = 16 dB
66
I&Q Gain Mismatch
Without calibration
-0.3 0.3 dB
I&Q Phase Imbalance
Without calibration
-2 2 deg
Channel filter characteristics Passband ripple (peak-to-peak 0.3~8.5 MHz )
(after calibration)
Max group delay (peak-to-peak 0.3~8.5 MHz )
0.5 dB
50 ns
Attenuation @ freq >= 12 MHz
8
dB
Attenuation @ freq >= 15 MHz
25
dB
Attenuation @ freq >= 25 MHz
60
dB
CCK adjacent channel
attenuation @25 MHz
Referenced to in-band CCK signal power
50
dB
OFDM adjacent channel
attenuation @25 MHz
Referenced to in-band OFDM signal power
45
dB
3 dB DC blocking
frequency
After DC settling
10 kHz
Linear RSSI voltage output
RSSI slope
Input power –95 ~ -40 dBm. GS1GS2=11
Input power –90 ~ -22 dBm. GS1GS2=10
Input power –67 ~ 1 dBm. GS1GS2=01 or 00
Average RSSI voltage change per 1 dB input
level change
RSSI error
With OFDM short preamble
RSSI settling time
GS1GS2=11 change to GS1GS2=10 or 0x
while GS3=GS4=GS5=GS6=GS7=1
Resistive RSSI output load
Capacitive RSSI output load
TX to RX switching time
Output signal within 1 dB of final value with
CW input
Resistive I&Q output load Pin to ground/differential
Capacitive I&Q output load Pin to ground/differential
Nominal I&Q output level
With gain adjustment. Differential peak to
peak.
Output 1 dB compression Differential peak to peak
I&Q output DC offset
After DC cancellation
I&Q output common mode
0.7 2 V
0.4 2 V
0.4 2 V
23.5 mV
/dB
-3 3 dB
300 ns
10 kΩ
5 pF
2 us
5/10 kΩ
6/3 pF
1000
mVpp
1.5 Vpp
10 mV
1.2 V
Confidential
Doc. #: DS-2453-01 <Rev. 0.0>
Page 11/ 24
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