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PDF MOA2400D Data sheet ( Hoja de datos )
| Número de pieza | MOA2400D | |
| Descripción | Leader | |
| Fabricantes | Mathstar | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MOA2400D (archivo pdf) en la parte inferior de esta página. Total 70 Páginas | ||
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The FPOA™ Leader
Field Programmable Object Array™
Arrix™ Family
Product Data Sheet
www.mathstar.com
10.26.2006
1 page  
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Arrix Family Data Sheet
Table of Contents
List of Figures
www.mathstar.com
Figure 1-1: FPOA Core and Periphery . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 1-2: FPOA Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 2-1: Ball Pattern for XRAM (Top-down View) . . . . . . . . . . 14
Figure 2-2: XRAM Clock Routing Option #1 . . . . . . . . . . . . . . . . . 22
Figure 2-3: XRAM Clock Routing Option #2 . . . . . . . . . . . . . . . . . 22
Figure 2-4: XRAM Clock to Data Clock Timing . . . . . . . . . . . . . . . 26
Figure 2-5: XRAM Address and Control Timing . . . . . . . . . . . . . . . 26
Figure 2-6: XRAM MRS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 2-7: XRAM Data Write Timing . . . . . . . . . . . . . . . . . . . . . . 27
Figure 2-8: XRAM Write Latency . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 2-9: XRAM Data Read Timing . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 2-10: XRAM Read Latency. . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 2-11: XRAM Write Followed By Read Timing . . . . . . . . . . 29
Figure 2-12: RLDRAM Initialization Sequence . . . . . . . . . . . . . . . . 33
Figure 3-1: Ball Pattern for GPIO (Top-down View). . . . . . . . . . . . 36
Figure 3-2: GPIO Input Timing (Synchronous) . . . . . . . . . . . . . . . . 41
Figure 3-3: GPIO Output Timing (Synchronous) . . . . . . . . . . . . . . . 41
Figure 3-4: GPIO Output Tri-state Timing . . . . . . . . . . . . . . . . . . . . 41
Figure 4-1: Ball Pattern for RX (Top-down View). . . . . . . . . . . . . . 44
Figure 4-2: RX DDR In-Phase Timing . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 4-3: RX DDR 90º Phase-Shifted Timing. . . . . . . . . . . . . . . . 49
Figure 4-4: RX SDR In-Phase Timing . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 4-5: RX SDR 90º Phase-Shifted Timing . . . . . . . . . . . . . . . . 49
Figure 5-1: Ball Pattern for TX (Top-down View). . . . . . . . . . . . . . 52
Figure 5-2: TX DDR In-Phase Timing . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 5-3: TX DDR 90º Phase-Shifted Timing. . . . . . . . . . . . . . . . 57
Figure 5-4: TX SDR In-Phase Timing . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 5-5: TX SDR 90º Phase-Shifted Timing . . . . . . . . . . . . . . . . 58
Figure 6-1: Startup Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 6-2: Ball Pattern for Init & Control (Top-down View) . . . . . 62
Figure 6-3: Start of PROM Load Sequence . . . . . . . . . . . . . . . . . . . 65
Figure 6-4: Completion of PROM Load Sequence. . . . . . . . . . . . . . 65
Figure 6-5: Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 6-6: JTAG Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 6-7: PROM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 7-1: Input Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 7-2: Current Surge at Startup. . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 10-1: Package Dimensions – Top View . . . . . . . . . . . . . . . . 87
Figure 10-2: Package Dimensions – Side View . . . . . . . . . . . . . . . . 88
Figure 10-3: Package Dimensions – Bottom View. . . . . . . . . . . . . . 88
Figure 11-1: Ball Pattern for FPOA (Top-down View) . . . . . . . . . . 91
Arrix Family Field Programmable Object Array (FPOA)
3
5 Page 
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Arrix Family Data Sheet
Chapter 1 Introduction
Chapter 1
Introduction
General Description
MathStar™’s Field Programmable Object Array™ (FPOA™) is a
breakthrough field-programmable silicon platform that supports
high-speed designs. Unlike FPGAs, which implement functions at the
gate level, FPOAs employ higher-order building blocks called “objects.”
These objects provide a much higher level of abstraction than the gates
of conventional FPGAs and perform complex operations at very high
clock rates.
Each Arrix™ family FPOA contains over 400 objects that are able to pass
data and signals to each other through a patented, configurable
communication framework. The timing of both the objects and the
communication framework is fixed, operating deterministically at
frequencies of up to 1 GHz. This deterministic performance eliminates the
tedious timing closure design steps associated with previous silicon
solutions such as FPGAs and ASICs. MathStar’s FPOA allows high-level
functions, algorithms, equations, and block diagrams to be quickly,
directly, and efficiently realized in high-performance silicon.
The Arrix product family is comprised of six products as shown in
Table 1-1.
Table 1-1 Arrix Product Family
Product
Package Information
Maximum Operating Frequency
MOA2400D-10
HFCBGA-896
1 GHz
MOA2400D-08
HFCBGA-896
800 MHz
MOA2400D-04
MOA2400D-10 R
MOA2400D-08 R
MOA2400D-04 R
HFCBGA-896
HFCBGA-896, RoHS Complianta
HFCBGA-896, RoHS Complianta
HFCBGA-896, RoHS Complianta
400 MHz
1 GHz
800 MHz
400 MHz
a. RoHS (Restriction on Hazardous Substances) compliance requires limited levels of lead (Pb), mercury, cad-
mium, hexavalent chromium, polybrominated biphenyl (PBB), and polybrominated diphenyl ethers (PBDE).
These levels must be below thresholds proposed by the EU.
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Arrix Family Field Programmable Object Array (FPOA)
9
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet MOA2400D.PDF ] | |
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