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PDF E8870DH Data sheet ( Hoja de datos )
| Número de pieza | E8870DH | |
| Descripción | Intel E8870DH DDR Memory Hub | |
| Fabricantes | Intel Corporation | |
| Logotipo |  |
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Intel® 82870DH DDR Memory Hub (DMH)
Datasheet
Product Features
s Two independent DDR DIMM channels
per DMH.
— 4 DIMMs per DDR Channel.
— Registered PC1600 DDR DIMMs.
s Write Buffers to minimize large turnaround
times.
s Pass through architecture for Read and
Write accesses.
s Supports 128 Mb, 256 Mb, 512 Mb and
1 Gb DDR SDRAM technologies.
s Each DMH supports a wide range of
memory size.
— Up to 4 GB using 128 Mb device.
— Up to 8 GB using 256 Mb device.
— Up to 16 GB using 512 Mb device.
— Up to 32 GB using 1 Gb device.
s Support of RDRAM CMOS signals to
facilitate initialization and read/write of
registers.
s DMH internal registers accessed through
CMOS signal interface.
s Tunnels DDR SDRAM protocol over RSL.
s Integrated System Management Bus (SMB)
controller to read and write data from/to
SPD EEPROM on the DIMMs.
s 1.6 GB/s data rates in either 16-byte or
32-byte DDR DIMM transfer mode.
s 567 pin OLGA package.
Document Number: 251113-001
August 2002
1 page  
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6 Ballout and Package Information ....................................................................................6-1
6.1 567-Ball OLGA1 Package Information ...............................................................6-1
6.2 Ballout Signal List...............................................................................................6-4
7 Testability ........................................................................................................................7-1
7.1 Parametric Test Mode ........................................................................................7-1
Figures
1-1
1-2
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
5-1
5-2
6-1
6-2
6-3
Fully Loaded SNC Example ...............................................................................1-1
DMH Driving Both DIMM Channels, Four DIMMs per Channel .........................1-2
DMH Block Diagram...........................................................................................4-2
Driving MCP to DIMM Address and Control Lines .............................................4-3
Phase Shifted MCP Command State Tracker and Correction ...........................4-4
Example of Valid Write Command Ordering ......................................................4-8
DRCG Connection Diagram .............................................................................4-10
Register Read MSIO Transaction ....................................................................4-10
Register Write MSIO Transaction.....................................................................4-11
MSIO Register Read Transaction ....................................................................4-12
MSIO Register Write Transaction.....................................................................4-12
Connection of DIMM Serial I/O Signals............................................................4-13
Random Byte Read Timing ..............................................................................4-14
Byte Write Register Timing...............................................................................4-15
PWRGOOD Sequence Method 1.....................................................................4-16
PWRGOOD Sequence Method 2.....................................................................4-17
SIO Reset Sequence........................................................................................4-17
SSTL-2 Common Clock AC Timing....................................................................5-5
SSTL-2 Source Synchronous AC Timing ...........................................................5-6
567-Ball (DMH) OLGA1 Package Dimensions – Top View................................6-1
567-Ball (DMH) OLGA1 Package Dimensions – Bottom View...........................6-2
567-Ball (DMH) OLGA1 Solder Balls Detail .......................................................6-3
Tables
1-1
2-1
2-2
2-3
2-4
3-1
4-1
4-2
4-3
4-4
4-5
5-1
5-2
5-3
5-4
5-5
5-7
5-6
5-8
Memory Size ......................................................................................................1-3
Main Channel Interface Signals .........................................................................2-1
Branch Channel Interface Signals......................................................................2-2
Reset and Miscellaneous Signals ......................................................................2-3
Voltage Reference Signals.................................................................................2-4
Unified Access Register Definitions .................................................................3-11
Encoding of ST and SF ......................................................................................4-3
Write Buffer Burst Operation for Read-Hit Operations .......................................4-9
MSIO Packet Field Definitions..........................................................................4-11
SCK Clock Divider Frequency Table................................................................4-14
DDR SDRAM Command Encoding for SDI Register .......................................4-16
Absolute Maximum Non-Operational DC Ratings at the Package Pin...............5-1
Voltage and Current Specifications ....................................................................5-1
DMH Main Channel Signal Groups ....................................................................5-2
Main Channel Vref Specification ........................................................................5-2
RSL Data Group, DC Parameters ......................................................................5-2
Main Channel “CMOS 1.8 I/O” DC Parameters .................................................5-3
RSL Clocks, DC Parameters..............................................................................5-3
DMH DDR Signal Groups...................................................................................5-3
Intel® E8870DH DDR Memory Hub (DMH) Datasheet
v
5 Page 
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Signal Description
2
The following notations are used to describe the signal types and their drive state:
• I Input pin
• O Output pin
• I/O Bidirectional input/output pin
• Z Tri-stated
• L Driven low
• H Driven high
• ? Output state is indeterminate
2.1 Main Channel Interface
The Main Channel is the interface between the SNC and DMH.
Table 2-1. Main Channel Interface Signals
Signal
Type
State during
PWRGOOD
Deassertion
Description
DQA[8:0]
DQB[8:0]
RQ[7:0]
SIO
SCK
CMD
CTM
CTMN
I/O
RSL
I/O
RSL
I
RSL
I/O
CMOS
1.8V
I
CMOS
1.8V
I
CMOS
1.8V
I
RSL
I
RSL
? Data Bus, Data Byte A:
Bidirectional 9-bit data bus A. These correspond to the
DQA[8:0] signals on the RAC.
? Data Bus, Data Byte B:
Bidirectional 9-bit data bus B. These correspond to the
DQB[8:0] signals on the RAC.
I Request Control:
These signals carry the memory control packets (MCP)
from the SNC to the DMH. These correspond to the
RRq[2:0] and CRq[4:0] signals on the RAC.
I Serial I/O Chain:
Serial input/output pins used for reading and writing
control registers.
I Serial Clock:
Clock source used for timing of the SIO and CMD
signals. This corresponds to the SCK signal on the RAC.
I Serial Command:
Serial command input used for control register read and
write operations. This corresponds to the CMD signal on
the RAC.
I Clock to RAC Master:
One of the two differential transmit clock signals used for
DMH to RAC Master operations.
I Clock to RAC Master Complement:
One of the two differential transmit clock signals used for
DMH to RAC Master operations.
Intel® E8870DH DDR Memory Hub (DMH) Datasheet
2-1
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