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PDF ML145407 Data sheet ( Hoja de datos )
| Número de pieza | ML145407 | |
| Descripción | 5 Volt Only Driver/Receiver | |
| Fabricantes | LANSDALE Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ML145407 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
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ML145407
5 Volt Only Driver/Receiver
RS232 EIA–232–E and CCITT V.28
Legacy Device: Motorola MC145407
The ML145407 is a silicon–gate CMOS IC that combines three
drivers and three receivers to fulfill the electrical specifications of
RS232 EIA–232–E and CCITT V.28 while operating from a single + 5
V power supply. A voltage doubler and inverter convert the + 5V to ±
10 V. This is accomplished through an on–board 20 kHz oscillator
and four inexpensive external electrolytic capacitors. The three drivers
and three receivers of the ML145407 are virtually identical to those of
the ML145406. Therefore, for applications requiring more than three
drivers and/or three receivers, an ML145406 can be powered from an
ML145407, since the ML145407 charge pumps have been designed to
guarantee ± 5 V at the output of up to six drivers. Thus, the
ML145407 provides a high–performance, low–power, stand–alone
solution or, with the ML145406, a + 5 V only, high–performance
two–chip solution.
This device offers the following performance features:
• Operating Temperature Range = TA –40° to +85°C
Drivers
• ± 7.5 V Output Swing
• 300Ω Power–Off Impedance
• Output Current Limiting
• TTL and CMOS Compatible Inputs
• Slew Rate Range Limited from 4 V/µs to 30 V/µs
Receivers
• + 25 V Input Range
• 3 to 7 kΩ Input Impedance
• 0.8 V Hysteresis for Enhanced Noise Immunity
Charge Pumps
• + 5 V to ± 10 V Dual Charge Pump Architecture
• Supply Outputs Capable of Driving Three On–Chip Drivers and
Three Drivers on the ML145406 Simultaneously
• Requires Four Inexpensive Electrolytic Capacitors
• On–Chip 20 kHz Oscillator
20
1
P DIP 20 = RP
PLASTIC DIP
CASE 738
20
1
SOG 20 = -6P
SOG PACKAGE
CASE 751D
CROSS REFERENCE/ORDERING INFORMATION
PACKAGE
MOTOROLA
LANSDALE
P DIP 20
SOG 20
MC145407P ML145407RP
MC145407DW ML145407-6P
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
PIN ASSIGNMENT
C2+ 1
20 C1+
2
GND
3
C2–
4
VSS
Rx1 5 R
19
VCC
18
C1–
17
VDD
16
DO1
6
Tx1
D 15 DI1
Rx2 7 R
14
DO2
Tx2 8
D 13 DI2
Rx3 9 R
12 DO3
10
Tx3
D 11 DI3
D = DRIVER
R = RECEIVER
Page 1 of 8
www.lansdale.com
Issue A
1 page  
ML145407
www.DataSheet4U.com
17 19
VDD VCC
15 6
DI1 Tx1
13 DI2
Tx2 8
Vin = ± 2 V
11 DI3
Tx3 10
VSS GND
42
Rout
=
Vin
I
Figure 1. Power–Off Source Resistance
DRIVERS
DI1 – DI3
50%
tf
Tx1 – Tx3
90%
10%
tPHL tPLH
3V
0V
tr
VOH
VOL
RECEIVERS
Rx1 – Rx3
50%
90%
DO1 – DO3
tPHL
50%
10%
tf
+3V
0V
tPLH
VOH
VOL
tr
Figure 2. Switching Characteristics
DRIVERS
Tx1 – Tx3
3V
–3V
tSLH
3V
–3V
tSHL
SLEW RATE (SR) = – 3 V – (3 V) OR 3 V – ( – 3 V)
tSLH tSHL
Figure 3. Slew Rate Characterization
LANSDALE Semiconductor, Inc.
PIN DESCRIPTIONS
VCC
Digital Power Supply (Pin 19)
The digital supply pin, which is connected to the logic pow-
er supply. This pin should have a 0.33 µF capacitor to ground.
GND
Ground (Pin 2)
Ground return pin is typically connected to the signal ground
pin of the EIA–232–E connector (Pin 7) as well as to the logic
power supply ground.
VDD
Positive Power Supply (Pin 17)
This is the positive output of the on–chip voltage doubler and
the positive power supply input of the driver/receiver sections of
the device. This pin requires an external storage capacitor to fil-
ter the 50% duty cycle voltage generated by the charge pump.
VSS
Negative Power Supply (Pin 4)
This is the negative output of the on–chip voltage
doubler/inverter and the negative power supply input of the
driver/receiver sections of the device. This pin requires an
external storage capacitor to filter the 50% duty cycle voltage
generated by the charge pump.
C2+, C2–, C1–, C1+
Voltage Doubler and Inverter (Pins 1, 3, 18, 20)
These are the connections to the internal voltage doubler and
inverter, which generate the VDD and VSS voltages.
Rx1, Rx2, Rx3
Receive Data Input (Pins 5, 7, 9)
These are the EIA–232–E receive signal inputs. A voltage
between + 3 and + 25 V is decoded as a space and causes the
corresponding DO pin to swing to ground (0 V). A voltage
between – 3 and – 25 V is decoded as a mark, and causes the
DO pin to swing up to VCC.
DO1, DO2, DO3
Data Output (Pins 16, 14, 12)
These are the receiver digital output pins, which swing from
VCC to GND. Each output pin is capable of driving one
LSTTL input load.
DI1, DI2, DI3
Data Input (Pins 15, 13, 11)
These are the high impedance digital input pins to the driv-
ers. Input voltage levels on these pins must be between VCC
and GND.
Tx1, Tx2, Tx3
Transmit Data Output (Pins 6, 8, 10)
These are the EIA–232–E transmit signal output pins,which
swing toward VDD and VSS. A logic 1 at a DI input causes the
corresponding Tx output to swing toward VSS. A logic 0 caus-
es the output to swing toward VDD. The actual levels and slew
rate achieved will depend on the output loading (RL\\CL).
Page 5 of 8
www.lansdale.com
Issue A
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet ML145407.PDF ] | |
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