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PDF ML145405 Data sheet ( Hoja de datos )

Número de pieza ML145405
Descripción (ML145403 - ML145408) Drivers/Receivers
Fabricantes LANSDALE Semiconductor 
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ML145403 ML145405
ML145404 ML145408
Drivers/Receivers
RS 232/EIA–232–E and CCITT V.28
Legacy Device: Motorola MC145403, MC145404, MC145405, MC145408
These devices are silicon gate CMOS ICs that combine both the
transmitter and receiver to fulfill the electrical specifications of EIA
Standard 232–E and CCITT V.28. The drivers feature true TTL input
compatibility, slew rate limiting outputs, 300 power–off source
impedance, and output typically switching to within 25% of the sup-
ply rails. The receivers can handle up to ± 25 V while presenting 3 to
7 kimpedance. Hysteresis in the receivers aid in the reception of
noisy signals. By combining both drivers and receivers in a single
CMOS chip, these devices provide efficient, low–power solutions for
both EIA–232–E and V.28 applications.
These devices offer the following performance features:
• Operating Temperature Range TA = –40° to +85°C
Drivers
• ± 5 to ± 12 V Supply Range
• 300 Power–Off Source Impedance
• Output Current Limiting
• TTL and CMOS Compatible Inputs
• Driver Slew Rate Range Limited to 30 V/µs Maximum
Receivers
• ± 25 V Input Range
• 3 to 7 kInput Impedance
• 0.8 V of Hysteresis for Enhanced Noise Immunity
• TTL and CMOS Compatible Outputs
Available Driver/Receiver Combinations
Device
Drivers Receivers Figure
ML145403
3
5
1
ML145404
4
4
2
ML145405
5
3
3
ML145408
5
5
4
No. of Pins
20
20
20
24
Alternative EIA–232 devices to consider are:
Three Supply
Single Supply
ML145406 (3 x 3)
ML145407 (3 x 3)
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
Page 1 of 8
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Issue A

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ML145405 pdf
LANSDALE Semiconductor, Inc.
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ML145403, ML145404, ML145405, ML145408
1 24
22 VDD VCC 3
DI1 Tx1
20
DI2
5
Tx2
18
DI3
7
Tx3
16
DI4
9
Tx4
14
DI5
VDD
12
11
Tx5
GND
13
Vin = ± 2 V
Rout
Vin
I
DRIVERS
DI 50%
Tx 90%
tPHL
tf
10%
RECEIVERS
Rx 50%
tPHL
90%
DO 10%
tf
Figure 1. Power–Off Source Resistance
Illustrated for ML145408
+3V
0V
tr
VOH
VOL
tPLH
+3V
0V
tPLH
VOH
VOL
tr
DRIVERS
+3V
Tx
–3V
tSHL
+3V
–3V
tSLH
Slew Rate =
6V
tSLH or tSHL
Figure 2. Switching Characteristics
Figure 3. Slew Rate Characteristics
PIN DESCRIPTIONS
VCC
Digital Power Supply
The digital supply pin, which is connected to the logic power
supply (+ 5.5 V maximum).
GND
Ground
Ground return pin is typically connected to the signal ground
pin of the EIA–232–E connector (Pin 7) as well as to the logic
power supply ground.
VDD
Most Positive Device Pin
The most positive power supply pin, which is typically + 5 to
+ 12 V.
VSS
Most Negative Device Pin
The most negative power supply pin, which is typically – 5 to – 12 V.
Rx1 – Rxn
Receive Data Input Pins
These are the EIA–232–E receive signal inputs. A voltage
between + 3 and + 25 V is decoded as a space, and causes the
corresponding DO pin to swing to ground (0 V). A voltage
between – 3 and – 25 V is decoded as a mark, and causes the
corresponding DO pin to swing to VCC.
DO1 – DOn
Data Output Pins
These are the receiver digital output pins which swing
fromVCC to GND. Each output pin is capable of driving one
LSTTL input load.
Page 5 of 8
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Issue A

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