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PDF ML145583 Data sheet ( Hoja de datos )

Número de pieza ML145583
Descripción 3.3 Volt Only Driver/Receiver
Fabricantes LANSDALE Semiconductor 
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ML145583
3.3 Volt Only Driver/Receiver with
an Integrated Standby Mode
RS 232/EIA–232–E and CCITT V.28
Legacy Device: Motorola MC145583
The ML145583 is a CMOS transceiver composed of three drivers and
five receivers that fulfills the electrical specifications of EIA–232–E,
EIA–562, and CCITT V.28 while operating from a single + 3.3 or + 5.0 V
power supply. This transceiver is a high–performance, low–power con-
sumption device that is equipped with a standby function.
A voltage tripler and inverter converts the + 3.3 V to ± 8.8 V, or a volt-
age doubler and inverter converts the + 5.0 V to ± 8.8 V. This is accom-
plished through an on–chip 40 kHz oscillator and five inexpensive exter-
nal capacitors.
FEATURES
Drivers:
• ± 5 V Minimum Output Swing at 3.3 or 5.0 V Power Supply
• 300 Power–Off Impedance
• Output Current Limiting
• Three–State Outputs During Standby Mode
Receivers:
• ± 25 V Input Range
• 3 to 7 kInput Impedance
• 0.8 V Hysteresis for Enhanced Noise Immunity
• Three–State Outputs During Standby Mode
Ring Monitor Circuit:
• Invert the Input Level on Rx1 to Logic Output Level on RIMON at
Standby Mode
28
1
SOIC 28W = -7P
SOG PACKAGE
CASE 751F
PACKAGE
SOIC 28W
MOTOROLA
LANSDALE
MC145583DW ML145583-7P
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
PIN ASSIGNMENT
C5+ 1
28 C2+
GND 2
27 VCC
C5– 3
RIMON 4
VSS 5
STB 6
Rx1 7
Rx2 8
Rx3 9
Tx1 10
Rx4 11
Tx2 12
Rx5 13
Tx3 14
26 C2–
RING
MONITOR
CIRCUIT
(INVERTING)
25
24
C1+
C1–
23 VDD
22 DO1
21 DO2
20 DO3
19 DI1
18 DO4
17 DI2
16 DO5
15 DI3
Page 1 of 7
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Issue A

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ML145583 pdf
LANSDALE Semiconductor, Inc.
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ML145583
PIN DESCRIPTIONS
VCC
Digital Power Supply (Pin 27)
This digital supply pin is connected to the logic power supply. This
pin should have a not less than 0.33 µF capacitor GND.
GND
Ground (Pin 2)
Ground return pin is typically connected to the signal ground pin of
the EIA–232–E connector (Pin 7) as well as to the logic power sup-
ply ground.
VDD
Positive Power Supply (Pin 23)
This is the positive output of the on–chip voltage tripler and the
positive power supply input of the driver/receiver sections of the
device. This pin requires an external storage capacitor to filter the
50% duty cycle voltage generated by the charge pump.
VSS
Negative Power Supply (Pin 5)
This is the negative output of the on–chip voltage tripler/inverter
and the negative power supply input of the driver/ receiver sections
of the device. This pin requires an external storage capacitor to filter
the 50% duty cycle voltage generated by the charge pump.
RIMON
Ring Monitor Circuit (Pin 4)
The Ring Monitor Circuit will convert the input level on Rx1 pin
at standby mode and output on the RIMON pin.
STB
Standby Mode (Pin 6)
The device enters the standby mode while this pin is connected to
the logic high level. During the standby mode, driver and receiver
output pins become high–impedance state. In this condition, supply
current ICC is below 5 µA (typ).
C5+, C5–, C2+, C2–, C1+, C1–
Voltage Tripler and Inverter (Pins 1, 3, 28, 26, 25, 24)
These are the connections to the internal voltage tripler and invert-
er, which generate the VDD and VSS voltages.
Rx1, Rx2, Rx3, Rx4, Rx5
Receive Data Inputs (Pins 7, 8, 9, 11, 13)
These are the EIA–232–E receive signal inputs. A voltage between
+ 3 and + 25 V is decoded as a space, and causes the corresponding
DO pin to swing to GND (0 V). A voltage between – 3 and – 25 V is
decoded as a mark, and causes the DO pin to swing up to VCC.
DO1, DO2, DO3, DO4, DO5
Data Outputs (Pins 22, 21, 20, 18, 16)
These are the receiver digital output pins, which swing from VCC
to GND. Output level of these pins is high impedance while in stand-
by mode.
DI1, DI2, DI3
Data Inputs (Pins 19, 17, 15)
These are the high impedance digital input pins to the drivers.
Input voltage levels on these pins must be betweenVCC and GND.
Tx1, Tx2, Tx3
Transmit Data Output (Pins 10, 12, 14)
These are the EIA–232–E transmit signal output pins, which
swing toward VDD and VSS. A logic 1 at a DI input causes the cor-
responding Tx output to swing toward VSS. The actual levels and
slew rate achieved will depend on the output loading (RL/CL). The
minimum output impedance is 300 when turned off.
DRIVER
DI1 – DI3
(INPUT)
50%
Tx1 – Tx3
(OUTPUT)
tf
90%
10%
tDPHL
tDPLH
RECEIVER
Rx1 – Rx5
(INPUT)
50%
DO1 – DO5
(OUTPUT)
tRPHL
90%
10%
tf
SWITCHING CHARACTERISTICS
+3V
0V
tr
VOH
VOL
DRIVER
STB (INPUT)
Tx1 – Tx3
(OUTPUT)
tDAZ
+ 1.5 V
+5V
–5V
+3V
0V
tRPLH
VOH
VOL
tr
RECEIVER
STB (INPUT)
DO1 – DO5
(OUTPUT)
tRAZ
+ 1.5 V
90%
10%
HIGH Z
tDZA
+ 1.5 V
+ 3.3 V
0V
+ 5 V VOH
– 5 V VOL
HIGH Z
tRZA
+ 1.5 V
90%
+ 3.3 V
0V
VOH
10% VOL
Page 5 of 7
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Issue A

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