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PDF ATSAM9743 Data sheet ( Hoja de datos )
| Número de pieza | ATSAM9743 | |
| Descripción | Sound Synthesis Single-chip Music System | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Integrates a 64-slot Digital Signal Processor (DSP), 16-bit Processor, 24K x 16 On-chip
Flash Memory, 2K x 16 RAM, 64 Individually Programmable I/O Pins
• Alternate Group Selectable I/O Pins Allow External Memory Expansion, Host Parallel
I/O, Serial MIDI_IN/MIDI_OUT, Additional Digital Audio-in/out
• Up to 64 Voices Polyphony, 24 dB Resonant Filter Per Voice, User Programmable
Synthesis/Processing Algorithms
• Three Timers, One Timer Being Available for Orchestrations Tempo Control
• Ideal for Battery Operation
• 3V to 4.5V Power Supply
• Power-down Mode
• Parameters Can Be Saved Into Built-in Flash Memory on a Single Word Write Basis.
• Compatible with ATSAM97xx Series Design Tools and Debugger
• Quick Time to Market
www.Data•ShPereot4vUe.ncoRmeliable Synthesis Drivers
• In-circuit Emulation with Code View Debugger for Easy Prototype Development
• Built-in Flash Programming Algorithm
• Low frequency Input Clock at 256xFs Minimizes RFI, Built-in PLL Raises Frequency
Internally
• PQFP100 Easy Mount Standard Package (Pitch 0.65 mm)
• Atmel Standard Flash Technology
Description
The ATSAM9743 integrates into a single chip an ATSAM97xx core (64-slot DSP + 16-
bit processor), a 24K x 16 Flash memory, a 2K x 16 RAM, and up to 64 individually
programmable I/O pins. With the addition of a single external digital-to-analog con-
verter or a codec, the ATSAM9743 can be used in a variety of musical and sound
processing applications, like low-cost keyboards, equalizers and effect processors.
I/O pins can be configured for external memory expansion, allowing more sophisti-
cated products with up to 4M bytes RAM or ROM.
Figure 1. Typical Application of the ATSAM9743
Sound
Synthesis
ATSAM9743
Single-chip
Music System
Keyboard
Switches
LEDS
LCD Display
MIDI_IN/MIDI_OUT
ATSAM9743
DAC
Rev. 1773B-DRMSD–11/02
1
1 page  
ATSAM9743
Pin Description
Pins by Function
Table 1. Power Supply
Pin Name
Pin Number
Type
Function
GND
5, 10, 18, 22, 33, 45, 47, 59, 62, 75, 88, 99
PWR
Digital Ground: All pins should be connected to a
ground plane
VC3 3, 11, 21, 27, 61
PWR
Core Power Supply, 3V to 3.8V:
All pins should be connected
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17, 31, 46, 57, 73, 87, 100
PWR
I/O Power Supply, 3V to 5.5V:
All pins should be connected to a VCC plane
Note:
Power supply decoupling: Like all high speed HCMOS ICs, proper decoupling is mandatory for reliable operation and RFI reduc-
tion. The recommended decoupling is 100 nF at each corner of the IC with an additional 10 µFT bulk capacitor close to the X1,
X2 pins.
Table 2. Single Function Pins
Pin Name
Pin Number
Type
Function
CLBD
26
OUT
External DAC serial bit clock
WSBD
37
OUT
External DAC left/right clock
DABD0
35
OUT
External DAC serial stereo audio data
P3.12 - P3.14 81, 23, 24
Programmable General purpose I/O
X1 13
IN Crystal connection, or external clock input at
256*Fs, Fs being the sampling frequency. When
used as an input, a 330 ohms serial resistor
should be inserted. Typical crystal frequency is
8 MHz (Fs = 32 kHz)
X2 14
OUT
Other end of crystal connection. Cannot be used
to drive external circuitry.
CKOUT
95
OUT
Buffered X2 output, can be used to drive external
circuits, such as Sigma/Delta DACs
LFT 12
Analog
Built-in PLL compensation filter input
RESET
15
IN Master reset, active low, has built-in Schmitt
trigger.
PDWN
16
IN Power down, active low
TEST[2:0]
42 - 44
IN Test pins. Should be grounded for normal
operation.
TEST0 is used to start the built-in debugger.
In this case TEST2 specifies the communication
baud rate.
Note: Pin names exhibiting an overbar (PDWN for example) indicate that the signal is active low.
1773B–DRMSD–11/02
5
5 Page 
ATSAM9743
External Ram
(8 bits)
Figure 5. 8-bit SRAM Read Cycle
WCS1
WA[20:0]
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WOE
WWE
RBS
WD[7:0]
tCSOE
tRC
tPOE
tACE
tORB
t tOE ACH
Low
tDF
High
Note: By setting the SRAM 8-bit in the P16 control word, external RAM can be configured to read 16-bit with 2 x 8-bit
accesses.
Figure 6. 8-bit SRAM Write Cycle
WCS1
WA[20:0]
tCSWE
t WC
WOE
WWE
RBS
WD[7:0]
t WP t WP
tAS
t tDW1 DH1
Low
tDW2
tDH2
High
1773B–DRMSD–11/02
11
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet ATSAM9743.PDF ] | |
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