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P521-49 fiches techniques PDF

PhaseLink Corporation - Low Phase Noise PECL VCXO

Numéro de référence P521-49
Description Low Phase Noise PECL VCXO
Fabricant PhaseLink Corporation 
Logo PhaseLink Corporation 





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P521-49 fiche technique
Preliminary P521-49
Low Phase Noise LVDS VCXO (27MHz to 65MHz)
FEATURES
27MHz to 65MHz Fundamental Mode Crystal.
Output range: 27MHz – 65MHz.
Complementary LVDS outputs.
Selectable OE Logic (enable high or enable low).
Integrated variable capacitors.
High pull linearity: < 5%.
www.DataSheet4U.+c/o-m125 ppm pull range
Supports 2.5V or 3.3V-Power Supply.
Available in die form.
Thickness 10 mil.
DESCRIPTIONS
P521-49 is a VCXO IC specifically designed to pull
high frequency fundamental crystals. Its internal
varicaps allow an on chip frequency pulling,
controlled by the VCON input. The chip provides a
low phase noise, low jitter LVDS differential clock
output.
BLOCK DIAGRAM
VCON Oscillator
Amplifier
X+
w/
integrated
varicaps
X-
OE
Q
Q
P521-49
DIE CONFIGURATION
57.5 mil
GNDOSC 18
17 16
VCON 19
XIN 20
XOUT 21
OE 22
1
2
(1460,1435)
15 14 13
12
11
34
10
9
8
7
56
VDDANA
VDDBUF
VDDBUF
PECLBAR
PECL
GNDBUF
Y (0,0)
X
DIE SPECIFICATIONS
Name
Size
Reverse side
Pad dimensions
Thickness
Value
56.5 x 57.5 mil
GND
80 micron x 80 micron
10 mil
OUTPUT ENABLE LOGIC SELECTION
OESEL
(Pad #14)
OECTRL
(Pad #22)
State
0 (Default)
0 Tri-state
1 (Default) Output enabled
1
0 (Default) Output enabled
1 Tri-state
Pad #14, 22: Bond to GND to set to “0”, bond to VDD to set to “1”
No connection results to “default” setting through internal pull-up/-down.
Pad #22: Logical states defined by CMOS VIH and VIL levels.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 3/02/04 Page 1

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