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PDF JS29F04G08AANB1 Data sheet ( Hoja de datos )
| Número de pieza | JS29F04G08AANB1 | |
| Descripción | (JS29FxxG08xANB1) SD74 NAND Flash Memory | |
| Fabricantes | Intel | |
| Logotipo |  |
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Intel® SD74 NAND Flash Memory
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Product Features
Datasheet
Single-level cell (SLC) Technology
Organization:
— Page size:
x8: 2,112 bytes (2,048 + 64 bytes)
— Block size: 64 pages (128K + 4K bytes)
— Plane size: 2,048 blocks
— Device size: 4Gb: 4,096 blocks; 8Gb: 8,192
blocks; 16Gb: 16,384 blocks
Read performance:
— Random read: 25µs (MAX)
— Sequential read: 25ns (MIN)
Write performance:
— Page program: 220µs (TYP)
— Block erase: 1.5ms (TYP)
Data Retention:
— 10 years
Endurance:
— 100,000 PROGRAM/ERASE cycles
First block (block address 00h):
— Guaranteed to be valid up to 1,000
PROGRAM/ERASE cycles
Vcc:
— 2.7V – 3.6V
Operating Temperature:
— –25 oC to 85 oC
Command set:
— Industry-standard basic NAND Flash
command set
Advanced Command Set:
— PROGRAM PAGE CACHE MODE
— PAGE READ CACHE MODE
— One-time programmable (OTP) commands
— Two-plane commands
— Interleaved die operation
— READ UNIQUE ID (contact factory)
— READ ID2 (contact factory)
— IwnittehrinnatlhDeaptlaanMeofvreo:mOwpehricahtiodnastasuisppreoartded
Operation status byte:
— Provides software method for detecting:
— Operation completion
— Pass/fail condition
— Write-protect status
Ready/busy# (R/B#) signal:
— PPrRoOvGidReAsMa ohrarEdRwAaSrEe cmyceltehocdomfoprledteiotencting
WP# signal:
— Write protect entire device
RESET:
— Required after power-up
Package Types:
— 48-pin TSOP Type 1
— 48-pin TSOP OCPL Type 1
Configuration:
# of Die # of CE# # of R/B# I/O
1 1 1 Common
2 2 2 Common
4 2 2 Common
Order Number: 312774-007US
8-Sep-2006
1 page  
Intel® SD74 NAND Flash Memory
Figures
1 Intel® SD74 NAND Flash Memory Functional Block Diagram........................................... 10
2 Memory Map: SD74 Device ....................................................................................... 11
3 Array Organization: JS29F04G08AANB1 and JS29F08G08CANB1 ................................... 12
4 Array Organization: JS29F16G08FANB1 ...................................................................... 13
5 Pin Assignment (Top View) 48-Pin TSOP...................................................................... 14
6 48-pin TSOP............................................................................................................ 16
7 48-pin TSOP OCPL.................................................................................................... 17
8 Time Constants........................................................................................................ 20
9 Minimum Rp............................................................................................................ 20
10 READY/BUSY# Open Drain ........................................................................................ 20
11 tRise and tFall.......................................................................................................... 21
www.DataSheet4U.com 12 tIol vs. Rp ............................................................................................................... 21
13 TC vs. Rp................................................................................................................ 22
14 AC Waveforms During Power Transitions ..................................................................... 23
15 AC Waveforms During Power Transitions ..................................................................... 25
16 PAGE READ Operation .............................................................................................. 31
17 Random Data Read Operation.................................................................................... 31
18 PAGE READ CACHE MODE ......................................................................................... 32
19 READ ID Operation................................................................................................... 33
20 Status Register Operation ......................................................................................... 36
21 PROGRAM and READ STATUS Operation...................................................................... 37
22 RANDOM DATA INPUT............................................................................................... 37
23 PROGRAM PAGE CACHE MODE Example ...................................................................... 38
24 INTERNAL DATA MOVE ............................................................................................. 39
25 INTERNAL DATA MOVE with RANDOM DATA INPUT ....................................................... 39
26 Block Erase Operation............................................................................................... 40
27 OTP DATA PROGRAM ................................................................................................ 41
28 OTP DATA PROTECT ................................................................................................. 42
29 OTP DATA READ Operation ........................................................................................ 43
30 TWO-PLANE PAGE READ ........................................................................................... 45
31 TWO-PLANE PAGE READ with RANDOM DATA READ ...................................................... 46
32 TWO-PLANE PROGRAM PAGE ..................................................................................... 47
33 TWO-PLANE PROGRAM PAGE with RANDOM DATA INPUT............................................... 47
34 TWO-PLANE PROGRAM PAGE CACHE MODE ................................................................. 49
35 TWO-PLANE INTERNAL DATA MOVE............................................................................ 50
36 TWO-PLANE INTERNAL DATA MOVE with RANDOM DATA INPUT...................................... 51
37 TWO-PLANE BLOCK ERASE Operation ......................................................................... 52
38 TWO-PLANE/MULTIPLE-DIE READ STATUS Cycle .......................................................... 53
39 Interleaved PROGRAM PAGE with R/B# Monitoring ....................................................... 54
40 Interleaved PROGRAM PAGE with Status Register Monitoring ......................................... 54
41 Interleaved PROGRAM PAGE CACHE MODE with R/B# Monitoring.................................... 54
42 Interleaved PROGRAM PAGE CACHE MODE with Status Register Monitoring...................... 55
43 Interleaved TWO-PLANE PROGRAM PAGE with R/B# Monitoring...................................... 55
44 Interleaved TWO-PLANE PROGRAM PAGE with Status Register Monitoring........................ 56
45 Interleaved TWO-PLANE PROGRAM PAGE CACHE MODE with R/B# Monitoring .................. 57
46 Interleaved TWO-PLANE PROGRAM PAGE CACHE MODE with Status Register Monitoring .... 57
47 Interleaved BLOCK ERASE with R/B# Monitoring .......................................................... 58
48 Interleaved BLOCK ERASE with Status Register Monitoring ............................................ 58
49 Interleaved TWO-PLANE BLOCK ERASE with R/B# Monitoring......................................... 59
50 Interleaved TWO-PLANE BLOCK ERASE with Status Register Monitoring........................... 59
51 RESET Operation...................................................................................................... 60
52 ERASE Enable.......................................................................................................... 60
53 ERASE Disable......................................................................................................... 61
8-Sep-2006
Order Number: 312774-007US
Intel® SD74 NAND FlasDhaMtaesmhoereyt
5
5 Page 
Intel® SD74 NAND Flash Memory
2.2.1
Figure 2.
Memory Map for the SD74 Device
Memory Map: SD74 Device
Blocks
4Gb,8Gb:BA[17:6] 0 1 2 • • • • • • • • •• • • 4,095
16Gb: BA[18:6]
16Gb:
8,192 blocks per CE#
www.DataSheet4U.com
Pages 0 1 2 • • • 63
PA[5:0]
Table 1.
Note:
2.2.2
Bytes 0 1 2 • • • • • • • • ••• • ••• • • •
CA[11:0]
2,047 • •• 2,111
Spare area
Operational Example: SD74 Device
Block Page Min Address in Page Max Address in Page Out of Bounds Addresses in Page
0 0 0x0000000000
0x000000083F
0x0000000840–0x0000000FFF
0 1 0x0000010000
0x000001083F
0x0000010840–0x0000010FFF
0 2 0x0000020000
0x000002083F
0x0000020840–0x0000020FFF
……
…
…
4,095 62
0x03FFFE0000
0x03FFFE083F
0x03FFFE0840–0x03FFFE0FFF
4,095 63
0x03FFFF0000
0x03FFFF083F
0x03FFFF0840–0x03FFFF0FFF
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AanrrdaJySO2r9gFa0n8izGa0t8ioCnANanBd1 Addressing for the JS29F04G08AANB1
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8-Sep-2006
Order Number: 312774-007US
Intel® SD74 NAND FlasDhaMtaesmhoereyt
11
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| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet JS29F04G08AANB1.PDF ] | |
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