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PDF iT4050D Data sheet ( Hoja de datos )
| Número de pieza | iT4050D | |
| Descripción | Dual LVDS-to-SCFL level translator | |
| Fabricantes | Iterra | |
| Logotipo |  |
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iT4050D
Dual LVDS-to-SCFL Level Translator
Description
www.DataSheet4U.com
The iT4050D is a wideband LVDS-to-SCFL level translator fabricated using 0.1μm HBT GaAs
technology. It is based on ECL topology to guarantee high-speed operation. The two translators
are fully independent, allowing power consumption to be optimized according to the application.
The device can translate NRZ streams with data rate up to 3.125 Gb/s or clock signals with a
frequency up to 3.125 GHz. The inputs and outputs of the iT4050D are DC coupled. At the input
side, internal 100-ohm resistors between the two differential lines avoid the need for external
impedance matching terminations. The input levels are fully compliant with LVDS specifications.
The iT4050D uses SCFL output levels and allows either single ended or differential data output.
The excellent rise and fall time and the good quality of the eye diagram at all data rates up to 3.125
Gb/s makes the iT4050D suitable for interfacing a generic LVDS output buffer with all iTerra SCFL
parts.
Features
Wideband signal handling: Up to 3.125 Gb/s NRZ Output fall time (20% – 80 %): <55 ps
Input sensitivity: 350 mV differential
100-ohm (differential) matched
450 mV pp typical single-ended output
DC-coupled inputs
Jitter RMS: <2 ps
50-ohm matched DC-coupled outputs
Output rise time (20% – 80 %): <55 ps
Differential or single-ended output
Power consumption: 140 mW per translator
Absolute
Maximum
Ratings
Stresses above those
listed under Absolute
Maximum Ratings may
cause permanent
damage to the device.
This is a stress rating
only; functional
operation of the device
at these or any other
conditions above those
indicated in the
operational section of
this document is not
implied. Exposure to
absolute maximum
rating conditions for
extended periods may
affect device reliability.
Symbol Parameters/conditions
VDD
VEE
VIH
VIL
TA
TSTG
Power supply voltage
Power supply voltage
Input voltage level, high level
Input voltage level, low level
Operating temperature range - die
Storage temperature
Min.
Max. Units
0
-3.63
0
0
-15
-65
2.75
0
2.4
2.4
125
150
V
V
V
V
ºC
ºC
www.iterrac.com
This is a Production data sheet. See “Product Status Definitions” on
Web site or catalog for product development status.
October 5, 2005 Doc. 4051 Rev 0
1
iTerra Communications
2400 Geng Road, Ste. 100, Palo Alto, CA 94303
Phone (650) 424-1937, Fax (650) 424-1938
1 page  
Pad Positions
and Chip
Dimensions
Chip size:
1400 μm ±10 μm
x 2900 μm ±10 μm
www.DataSheet4UC.cohmip thickness:
104 μm ±3 μm
Pad size:
100 μm x 100 μm
RF pad pitch:
150 μm
iT4050D
Dual LVDS-to-SCFL Level Translator
www.iterrac.com
This is a Production data sheet. See “Product Status Definitions” on
Web site or catalog for product development status.
October 5, 2005 Doc. 4051 Rev 0
5
iTerra Communications
2400 Geng Road, Ste. 100, Palo Alto, CA 94303
Phone (650) 424-1937, Fax (650) 424-1938
5 Page | ||
| Páginas | Total 5 Páginas | |
| PDF Descargar | [ Datasheet iT4050D.PDF ] | |
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