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Número de pieza | UDA1350AH | |
Descripción | IEC 958 audio DAC | |
Fabricantes | NXP Semiconductors | |
Logotipo | ||
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UDA1350AH
IEC 958 audio DAC
Preliminary specification
File under Integrated Circuits, IC01
1999 Dec 16
1 page Philips Semiconductors
IEC 958 audio DAC
Preliminary specification
UDA1350AH
5 ORDERING INFORMATION
TYPE
NUMBER
UDA1350AH
NAME
QFP44
PACKAGE
DESCRIPTION
plastic quad flat package; 44 leads (lead length 1.3 mm);
body 10 × 10 × 1.75 mm
www.DataSheet4U.com
6 BLOCK DIAGRAM
VERSION
SOT307-2
CLKOUT
TC TEST2 RTCB
VSSA VDDA
VDDA(DAC)
Vref
VOUTL VSSA(DAC) VOUTR
VDDA(PLL)
VSSA(PLL)
TEST1
32
31
34
29
CLOCK
AND
TIMING CIRCUIT
23 39 44
26 27
18 17 25 24 22
DAC
DAC
VDDD(C)
VSSD(C)
L3MODE
L3CLOCK
L3DATA
SELSTATIC
SPDIF0
SPDIF1
2
4
10
6
5
35
15
16
L3
INTERFACE
SLICER
IEC 958
DECODER
UDA1350AH
DATA
OUTPUT
INTERFACE
NOISE SHAPER
INTERPOLATOR
AUDIO FEATURE PROCESSOR 12 MUTE
DATA
INPUT
INTERFACE
1 RESET
SELCHAN
13
VDDD
VSSD
43
3
11, 14,
28, 38,
40, 41
21 30 42
33 37 36 7 8 9
19 20
MGS750
n.c.
PREEM1
BCKO WSO DATAO BCKI SELCLK
LOCK PREEM0
DATAI WSI SELSPDIF
1999 Dec 16
Fig.1 Block diagram.
5
5 Page Philips Semiconductors
IEC 958 audio DAC
Preliminary specification
UDA1350AH
8.5 Data path
The UDA1350AH data path consists of the slicer and the
IEC 958 decoder, the digital data output and input
interfaces, the audio feature processor, digital interpolator
and noise shaper and the digital-to-analog converters.
8.5.1 IEC 958 INPUT
www.DataSheTeht4eU.UcoDmA1350AH IEC 958 decoder can select one out of
two IEC 958 input channels. An on-chip amplifier with
hysteresis amplifies the IEC 958 input signal to CMOS
level (see Fig.4).
All 24 bits of data for left and right are extracted from the
input bitstream as well as several of the IEC 958 key
channel-status bits.
The extracted key parameters are:
• Pre-emphasis
• Audio sample frequency
• Two-channel PCM indicator
• Clock accuracy.
Both the lock indicator and the key channel status bits are
accessible via the L3 interface.
The UDA1350AH supports the following sample
frequencies and data bit rates:
• fs = 32.0 kHz, resulting in a data rate of 2.048 Mbits/s
• fs = 44.1 kHz, resulting in a data rate of 2.8224 Mbits/s
• fs = 48.0 kHz, resulting in a data rate of 3.072 Mbits/s.
The UDA1350AH supports timing level I, II and III as
specified by the IEC 958 standard.
8.5.2 DIGITAL DATA OUTPUT AND INPUT INTERFACE
The digital data interface enables the exchange of digital
data to and from an external signal processing device.
The digital output and input formats are identical by
design. The possible formats are (see Fig.5):
• I2S-bus with a word length of up to 24 bits
• LSB-justified with a word length of 16 bits
• LSB-justified with a word length of 20 bits
• LSB-justified with a word length of 24 bits.
Important: the edge of the WS signal must fall on the
negative edge of the BCK signal at all times for proper
operation of the input and output interface (see Fig.8).
In the static pin control mode the format is selected by
means of pins L3MODE and L3DATA. In the L3 control
mode the format defaults to the I2S-bus settings and is
programmable via the L3 interface.
The IEC 958 decoder provides the pre-emphasis
information from the IEC 958 input bitstream to pins
PREEM0 and PREEM1 and to the L3 interface register.
Controlling the de-emphasis is different for the two modes:
• Static pin control mode:
For IEC 958 input de-emphasis is automatically done,
but for I2S-bus input de-emphasis is not possible.
• L3 control mode:
– IEC 958 input: bit SPDSEL must be set to logic 1 and
de-emphasis is done automatically.
– I2S-bus input: bit SPDSEL must be set to logic 0 and
de-emphasis can be controlled via bits DE0
and DE1.
handbook, halfpage
75 Ω
10 nF
SPDIF0, 15,
SPDIF1 16
180 pF
UDA1350AH
MGS873
Fig.4 IEC 958 input circuit and typical application.
1999 Dec 16
11
11 Page |
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PDF Descargar | [ Datasheet UDA1350AH.PDF ] |
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