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PDF EP1C12Qxxx Data sheet ( Hoja de datos )
| Número de pieza | EP1C12Qxxx | |
| Descripción | Cyclone FPGA Family | |
| Fabricantes | Altera Corporation | |
| Logotipo |  |
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Section I. Cyclone FPGA
Family Data Sheet
www.DataSheet4U.com
This section provides designers with the data sheet specifications for
Cyclone® devices. The chapters contain feature definitions of the internal
architecture, configuration and JTAG boundary-scan testing information,
DC operating conditions, AC timing parameters, a reference to power
consumption, and ordering information for Cyclone devices.
This section contains the following chapters:
■ Chapter 1. Introduction
■ Chapter 2. Cyclone Architecture
■ Chapter 3. Configuration & Testing
■ Chapter 4. DC & Switching Characteristics
■ Chapter 5. Reference & Ordering Information
Revision History
Refer to each chapter for its own specific revision history. For information
on when each chapter was updated, refer to the Chapter Revision Dates
section, which appears in the complete handbook.
Altera Corporation
Section I–1
Preliminary
1 page  
Features
Cyclone devices are available in quad flat pack (QFP) and space-saving
FineLine® BGA packages (see Table 1–2 through 1–3).
Table 1–2. Cyclone Package Options & I/O Pin Counts
Device
EP1C3
EP1C4
EP1C6
EP1C12
EP1C20
100-Pin TQFP 144-Pin TQFP 240-Pin PQFP 256-Pin
324-Pin
400-Pin
(1) (1), (2) (1) FineLine BGA FineLine BGA FineLine BGA
65 104
249 301
98 185 185
173 185 249
233 301
Notes to Table 1–2:
(1) TQFP: thin quad flat pack.
PQFP: plastic quad flat pack.
(2) Cyclone devices support vertical migration within the same package (i.e., designers can migrate between the
EP1C3 device in the 144-pin TQFP package and the EP1C6 device in the same package)
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Vertical migration means you can migrate a design from one device to
another that has the same dedicated pins, JTAG pins, and power pins, and
are subsets or supersets for a given package across device densities. The
largest density in any package has the highest number of power pins; you
must use the layout for the largest planned density in a package to
provide the necessary power pins for migration.
For I/O pin migration across densities, cross-reference the available I/O
pins using the device pin-outs for all planned densities of a given package
type to identify which I/O pins can be migrated. The Quartus® II
software can automatically cross-reference and place all pins for you
when given a device migration list. If one device has power or ground
pins, but these same pins are user I/O on a different device that is in the
migration path,the Quartus II software ensures the pins are not used as
user I/O in the Quartus II software. Ensure that these pins are connected
to the appropriate plane on the board. The Quartus II software reserves
I/O pins as power pins as necessary for layout with the larger densities
in the same package having more power pins.
Altera Corporation
January 2007
1–3
Preliminary
5 Page 
Logic Elements
With the LAB-wide addnsub control signal, a single LE can implement a
one-bit adder and subtractor. This saves LE resources and improves
performance for logic functions such as DSP correlators and signed
multipliers that alternate between addition and subtraction depending
on data.
The LAB row clocks [5..0] and LAB local interconnect generate the LAB-
wide control signals. The MultiTrackTM interconnect's inherent low skew
allows clock and control signal distribution in addition to data. Figure 2–4
shows the LAB control signal generation circuit.
Figure 2–4. LAB-Wide Control Signals
Dedicated
LAB Row
Clocks
Local
Interconnect
6
Local
Interconnect
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Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
labclkena1
labclkena2
syncload
labclr2
addnsub
labclk1
labclk2
asyncload
or labpre
labclr1
synclr
Logic Elements
The smallest unit of logic in the Cyclone architecture, the LE, is compact
and provides advanced features with efficient logic utilization. Each LE
contains a four-input LUT, which is a function generator that can
implement any function of four variables. In addition, each LE contains a
programmable register and carry chain with carry select capability. A
single LE also supports dynamic single bit addition or subtraction mode
selectable by an LAB-wide control signal. Each LE drives all types of
interconnects: local, row, column, LUT chain, register chain, and direct
link interconnects. See Figure 2–5.
Altera Corporation
January 2007
2–5
Preliminary
11 Page | ||
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