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Silicon Laboratories - 48-Pin Mixed-Signal MCU

Numéro de référence C8051F230
Description 48-Pin Mixed-Signal MCU
Fabricant Silicon Laboratories 
Logo Silicon Laboratories 





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C8051F230 fiche technique
C8051F230
25 MIPS, 8 kB Flash, 48-Pin Mixed-Signal MCU
Analog Peripherals
Two comparators
- Programmable hysteresis
- Configurable to generate interrupts or reset
VDD Monitor and Brown-out Detector
On-Chip JTAG Debug
- On-chip emulation circuitry facilitates full-speed, non-intrusive, in-circuit
emulation
- Supports breakpoints, single stepping, watchpoints, inspect/modify
memory, and registers
- Superior performance to emulation systems using ICE-chips, target
pods, and sockets
- Fully compliant with IEEE 1149.1 specification
Supply Voltage: 2.7 to 3.6 V
www.DataSheet4U- .cToympical operating current: 9 mA at 25 MHz
- Typical stop mode current: <0.1 uA
High-Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of instructions in 1 or 2
system clocks
- Up to 25 MIPS throughput with 25 MHz system clock
- Expanded interrupt handler; up to 21 interrupt sources
Memory
- 256 bytes data RAM
- 8 kB Flash; in-system programmable in 512 byte sectors (512 bytes are
reserved)
Digital Peripherals
- 32 port I/O; all are 5 V tolerant
- Hardware SPI™ and UART serial ports available concurrently
- 3 general-purpose 16-bit counter/timers
- Dedicated watchdog timer; bidirectional reset
Clock Sources
- Internal programmable oscillator: 2–16 MHz
- External oscillator: Crystal, RC, C, or Clock
- Can switch between clock sources on-the-fly
48-Pin TQFP
- Temperature Range: –40 to +85 °C
VDD
VDD
GND
GND
NC
NC
NC
NC
TCK
TMS
TDI
TDO
RST
MONEN
XTAL1
XTAL2
Analog/Digital
Power
JTAG
Logic
VDD
Monitor
External
Oscillator
Circuit
Internal
Oscillator
Debug HW
8
0
5Reset
1
WDT
System Clock
C
o
r
e
8 kB FLASH
256 byte
RAM
SFR Bus
Port 0
Latch
UART
P
0
Timer 0
Timer 1
Timer 2
M
U
X
Port 1
Latch
CP0 CP0
CP1 CP1
CP0+
CP0-
CP1+
CP1-
P
1
M
U
X
SYSCLK
Port 2
Latch
SPI
P
2
M
U
X
Port 3
Latch
P
0
P0.0/TX
P0.1/RX
P0.2//INT0
P0.3//INT1
D P0.4/T0
r
v
P0.5/T1
P0.6/T2
P0.7/T2EX
P
1
P1.0/CP0+
P1.1/CP0-
P1.2/CP0
P1.3/CP1+
D P1.4/CP1-
r
v
P1.5/CP1
P1.6/SYSCLK
P1.7
P
2
P2.0/SCK
P2.1/MISO
P2.2/MOSI
P2.3/NSS
D P2.4
r
v
P2.5
P2.6
P2.7
P
3
P3.0
P3.1
P3.2
P3.3
D P3.4
r
v
P3.5
P3.6
P3.7
General Purpose
Copyright © 2004 by Silicon Laboratories
6.15.2004

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