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PDF H8S2141B Data sheet ( Hoja de datos )
| Número de pieza | H8S2141B | |
| Descripción | 16-Bit Single-Chip Microcomputer | |
| Fabricantes | Renesas Technology | |
| Logotipo |  |
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To all our customers
Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand
names are mentioned in the document, these names have in fact all been changed to Renesas
Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and
corporate statement, no changes whatsoever have been made to the contents of the document, and
these changes do not constitute any alteration to the contents of the document itself.
Renesas Technology Home Page: http://www.renesas.com
www.DataSheet4U.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
1 page  
General Precautions on Handling of Product
1. Treatment of NC Pins
Note: Do not connect anything to the NC pins.
The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.
2. Treatment of Unused Input Pins
Note: Fix all unused input pins to high or low level.
Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a pass-
through current flows internally, and a malfunction may occur.
3. Processing before Initialization
Note:
When power is first supplied, the product’s state is undefined.
The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
www.DataSheeutn4dUef.icnoedmstate. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.
4. Prohibition of Access to Undefined or Reserved Addresses
Note: Access to undefined or reserved addresses is prohibited.
The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system’s
operation is not guaranteed if they are accessed.
Rev. 2.0, 08/02, page iii of xxxviii
5 Page 
5.3.7 Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR)
Wake-Up Event Interrupt Mask Register (WUEMRB)........................................92
5.4 Interrupt Sources ...............................................................................................................94
5.4.1 External Interrupts................................................................................................94
5.4.2 Internal Interrupts.................................................................................................96
5.5 Interrupt Exception Handling Vector Table ......................................................................96
5.6 Interrupt Control Modes and Interrupt Operation .............................................................99
5.6.1 Interrupt Control Mode 0 .....................................................................................99
5.6.2 Interrupt Control Mode 1 .....................................................................................101
5.6.3 Interrupt Exception Handling Sequence...............................................................103
5.6.4 Interrupt Response Times.....................................................................................105
5.6.5 DTC Activation by Interrupt ................................................................................106
5.7 Address Break ...................................................................................................................107
5.7.1 Features ................................................................................................................107
5.7.2 Block Diagram .....................................................................................................108
5.7.3 Operation..............................................................................................................108
5.7.4 Usage Notes..........................................................................................................109
5.8 Usage Notes.......................................................................................................................111
5.8.1 Conflict between Interrupt Generation and Disabling..........................................111
5.8.2 Instructions that Disable Interrupts ......................................................................111
5.8.3 Interrupts during Execution of EEPMOV Instruction ..........................................112
www.DataShe5e.8t.44U.cSoemtting on Product Incorporating DTC.................................................................112
5.8.5 IRQ Status Register (ISR) ....................................................................................112
Section 6 Bus Controller....................................................................................113
6.1 Features .............................................................................................................................113
6.2 Input/Output Pins ..............................................................................................................114
6.3 Register Descriptions.........................................................................................................114
6.3.1 Bus Control Register (BCR).................................................................................115
6.3.2 Wait State Control Register (WSCR)...................................................................116
6.4 Bus Control .......................................................................................................................117
6.4.1 Bus Specifications ................................................................................................117
6.4.2 Advanced Mode ...................................................................................................118
6.4.3 Normal Mode .......................................................................................................118
6.4.4 I/O Select Signals .................................................................................................119
6.5 Basic Bus Interface............................................................................................................120
6.5.1 Data Size and Data Alignment .............................................................................120
6.5.2 Valid Strobes ........................................................................................................121
6.5.3 Basic Operation Timing .......................................................................................122
6.5.4 Wait Control.........................................................................................................130
6.6 Burst ROM Interface .........................................................................................................131
6.6.1 Basic Operation Timing .......................................................................................131
6.6.2 Wait Control.........................................................................................................132
Rev. 2.0, 08/02, page ix of xxxviii
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| PDF Descargar | [ Datasheet H8S2141B.PDF ] | |
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