|
|
PDF CY14E064L Data sheet ( Hoja de datos )
| Número de pieza | CY14E064L | |
| Descripción | 64 Kbit (8K x 8) nvSRAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CY14E064L (archivo pdf) en la parte inferior de esta página. Total 17 Páginas | ||
|
No Preview Available !
CY14E064L
64 Kbit (8K x 8) nvSRAM
Features
■ 25 ns and 45 ns access times
■ Hands off automatic STORE on power down with external
68 mF capacitor
■ STORE to QuantumTrap® non-volatile elements is initiated
by software, hardware or AutoStore on power down
■ RECALL to SRAM initiated by software or power up
www.DataShee■t4UUn.cliommited READ, WRITE and RECALL cycles
■ 10 mA typical ICC at 200 ns cycle time
■ 1,000,000 STORE cycles to QuantumTrap
■ 100 year data retention to QuantumTrap
■ Single 5V operation +10%
■ Commercial temperature
■ SOIC package
■ RoHS compliance
Functional Description
The Cypress CY14E064L is a fast static RAM with a
non-volatile element in each memory cell. The embedded
non-volatile elements incorporate QuantumTrap technology
producing the world’s most reliable non-volatile memory. The
SRAM provides unlimited read and write cycles, while
independent, non-volatile data resides in the highly reliable
QuantumTrap cell. Data transfers from the SRAM to the
non-volatile elements (the STORE operation) takes place
automatically at power down. On power up, data is restored to
the SRAM (the RECALL operation) from the non-volatile
memory. Both the STORE and RECALL operations are also
available under software control. A hardware STORE is
initiated with the HSB pin.
Logic Block Diagram
A5
A6
A7
A8
A9
A 11
A 12
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
Quantum Trap
128 X 512
STORE
STATIC RAM
ARRAY
128 X 512
RECALL
COLUMN I/O
COLUMN DEC
A0 A1 A2 A3 A4 A10
VCC
VCAP
POWER
CONTROL
STORE/
RECALL
CONTROL
HSB
SOFTWARE
DETECT
-A0 A12
OE
CE
WE
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-06543 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised August 7, 2007
[+] Feedback
1 page  
CY14E064L
chip is disabled. It is important that READ cycles and not WRITE
cycles are used in the sequence. It is not necessary that OE is
LOW for a valid sequence. After the tSTORE cycle time is fulfilled,
the SRAM is again activated for READ and WRITE operation.
Software RECALL
Data is transferred from the non-volatile memory to the SRAM
by a software address sequence. A software RECALL cycle is
initiated with a sequence of READ operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled READ operations is
performed:
www.DataSheet4U.com
1. Read address 0x0000, Valid READ
2. Read address 0x1555, Valid READ
3. Read address 0x0AAA, Valid READ
4. Read address 0x1FFF, Valid READ
5. Read address 0x10F0, Valid READ
6. Read address 0x0F0E, Initiate RECALL cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared, and then the non-volatile information is transferred
into the SRAM cells. After the tRECALL cycle time, the SRAM is
once again ready for READ and WRITE operations. The
RECALL operation does not alter the data in the non-volatile
elements.
Data Protection
The CY14E064L protects data from corruption during low
voltage conditions by inhibiting all externally initiated STORE
and WRITE operations. The low voltage condition is detected
when VCC is less than VSWITCH. If the CY14E064L is in a WRITE
mode (both CE and WE are low) at power up after a RECALL or
after a STORE, the WRITE is inhibited until a negative transition
on CE or WE is detected. This protects against inadvertent writes
during power up or brown out conditions.
Noise Considerations
The CY14E064L is a high speed memory. It must have a high
frequency bypass capacitor of approximately 0.1 µF connected
between VCC and VSS, using leads and traces that are as short
as possible. As with all high speed CMOS ICs, careful routing of
power, ground, and signals reduce circuit noise.
Low Average Active Power
CMOS technology provides the CY14E064L the benefit of
drawing significantly less current when it is cycled at times longer
than 50 ns. Figure 3 shows the relationship between ICC and
READ or WRITE cycle time. Worst case current consumption is
shown for both CMOS and TTL input levels (commercial temper-
ature range, VCC = 5.5V, 100% duty cycle on chip enable). Only
standby current is drawn when the chip is disabled. The overall
average current drawn by the CY14E064L depends on the
following items:
1. The duty cycle of chip enable
2. The overall cycle rate for accesses
3. The ratio of READs to WRITEs
4. CMOS versus TTL input levels
5. The operating temperature
6. The VCC level
7. IO loading
Figure 3. Current Versus Cycle Time (READ)
Figure 4. Current Versus Cycle Time (WRITE)
Document Number: 001-06543 Rev. *D
Page 5 of 17
[+] Feedback
5 Page 
CY14E064L
Switching Waveforms
Figure 5. SRAM Read Cycle 1: Address Controlled [4, 5, 14]
tRC
ADDRESS
www.DataSheDeQt4(UDA.cToAmOUT)
tAA
tOH
DATA VALID
ADDRESS
CE
OE
DQ (DATA OUT)
ICC
Figure 6. SRAM Read Cycle 2: CE Controlled [4,14]
tRC
tLZCE
tACE
tPD
tHZCE
tDOE
tLZOE
STANDBY
t PU
ACTIVE
tHZOE
DATA VALID
Note
14. HSB must remain HIGH during READ and WRITE cycles.
Document Number: 001-06543 Rev. *D
Page 11 of 17
[+] Feedback
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet CY14E064L.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CY14E064I | 64-Kbit (8 K x 8) Serial (I2C) nvSRAM | Cypress Semiconductor |
| CY14E064L | 64 Kbit (8K x 8) nvSRAM | Cypress Semiconductor |
| CY14E064PA | 64-Kbit (8 K x 8) SPI nvSRAM | Cypress Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |