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UT54ACS138 fiches techniques PDF

ETC - 3-Line to 8-Line Decoders/Demultiplexers

Numéro de référence UT54ACS138
Description 3-Line to 8-Line Decoders/Demultiplexers
Fabricant ETC 
Logo ETC 





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UT54ACS138 fiche technique
UT54ACS138/UT54ACTS138
Radiation-Hardened
3-Line to 8-Line Decoders/Demultiplexers
FEATURES
• radiation-hardened CMOS
- Latchup immune
• High speed
• Low power consumption
www.DataSheet4SUin.cgolme 5 volt supply
• Available QML Q or V processes
• Flexible package
- 16-pin DIP
- 16-lead flatpack
DESCRIPTION
The UT54ACS138 and the UT54ACTS138 3-line to 8-line de-
coders/demultiplexers are designed to be used in high-perfor-
mance memory-decoding or data-routing applications requiring
very short propagation delay times.
The conditions at the binary select inputs and the three enable
inputs select one of eight output lines. Two active-low and one
active-high enable inputs reduce the need for external gates of
inverters when expanding. A 24-line decoder can be implement-
ed without external inverters and a 32-line decoder requires only
one inverter. An enable input can be used as a data input for
demultiplexing applications.
The devices are characterized over full military temperature
range of -55 C to +125 C.
PINOUTS
A
B
C
G2A
G2B
G1
Y7
VSS
FUNCTION TABLE
ENABLE INPUTS
G1
G2A
G2B
XXH
LXX
XHX
HL L
HL L
HL L
HL L
HL L
HL L
HL L
HL L
SELECT INPUTS
CBA
XXX
XXX
XXX
LLL
L LH
LHL
L HH
HL L
HLH
HH L
HHH
Y0 Y1 Y2
HHH
HHH
HHH
L HH
HLH
HH L
HHH
HHH
HHH
HHH
HHH
16-Pin DIP
Top View
A 1 16 VDD
B 2 15 Y0
C 3 14 Y1
G2A 4 13 Y2
G2B 5 12 Y3
G1 6 11 Y4
Y7 7 10 Y5
VSS 8
9 Y6
16-Lead Flatpack
Top View
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
VDD
Y0
Y1
Y2
Y3
Y4
Y5
Y6
OUTPUT
Y3 Y4 Y5 Y6 Y7
HHHHH
HHHHH
HHHHH
HHHHH
HHHHH
HHHHH
L HHHH
H L HHH
HH L HH
HHHL H
HHHH L
71 RadHard MSI Logic

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