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UT54ACS10 fiches techniques PDF

ETC - triple three-input NAND gates

Numéro de référence UT54ACS10
Description triple three-input NAND gates
Fabricant ETC 
Logo ETC 





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UT54ACS10 fiche technique
UT54ACS10/UT54ACTS10
Radiation-Hardened
Triple 3-Input NAND Gates
FEATURES
radiation-hardened CMOS
- Latchup immune
High speed
Low power consumption
www.DataSheetS4Uin.gcolem5 volt supply
Available QML Q or V processes
Flexible package
- 14-pin DIP
- 14-lead flatpack
DESCRIPTION
The UT54ACS10 and the UT54ACTS10 are triple three-input
NAND gates. The circuits perform the Boolean functions
Y = A B C or Y = A + B + C in positive logic.
The devices are characterized over full military temperature
range of -55 C to +125 C.
FUNCTION TABLE
INPUTS
OUTPUT
ABCY
HHH L
L XXH
X L XH
XXLH
LOGIC SYMBOL
(1)
A1
(2)
B1
(13)
C1
(3)
A2
(4)
B2
(5)
C2
(9)
A3
(10)
B3
(11)
C3
(12) Y1
(6) Y2
(8) Y3
Note:.
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and
IEC Publication 617-12.
PINOUTS
A1
B1
A2
B2
C2
Y2
VSS
14-Pin DIP
Top View
A1 1 14 VDD
B1 2 13 C1
A2 3 12 Y1
B2 4 11 C3
C2 5 10 B3
Y2 6
9 A3
VSS 7
8 Y3
14-Lead Flatpack
Top View
1 14
2 13
3 12
4 11
5 10
69
78
VDD
C1
Y1
C3
B3
A3
Y3
LOGIC DIAGRAM
A1
B1
C1
A2
B2
C2
A3
B3
C3
Y1
Y2
Y3
17 RadHard MSI Logic

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