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PDF 74AHC2G241 Data sheet ( Hoja de datos )
| Número de pieza | 74AHC2G241 | |
| Descripción | Dual buffer/line driver | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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74AHC2G241; 74AHCT2G241
Dual buffer/line driver; 3-state
Rev. 3 — 13 May 2013
Product data sheet
1. General description
The 74AHC2G241; 74AHCT2G241 is a high-speed Si-gate CMOS device.
The 74AHC2G241; 74AHCT2G241 is a dual non-inverting buffer/line driver with 3-state
outputs. The 3-state outputs are controlled by the output enable inputs 1OE and 2OE. A
HIGH level at pin 1OE causes output 1Y to assume a high-impedance OFF-state. A LOW
level at pin 2OE causes output 2Y to assume a high-impedance OFF-state.
Schmitt-trigger action at all inputs makes the circuit highly tolerant for slower input rise
and fall times.
2. Features and benefits
Symmetrical output impedance
High noise immunity
ESD protection:
HBM JESD22-A114E: exceeds 2000 V
MM JESD22-A115-A: exceeds 200 V
CDM JESD22-C101C: exceeds 1000 V
Low power dissipation
Balanced propagation delays
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74AHC2G241DP 40 C to +125 C TSSOP8
74AHCT2G241DP
74AHC2G241DC 40 C to +125 C VSSOP8
74AHCT2G241DC
74AHC2G241GD 40 C to +125 C XSON8
74AHCT2G241GD
Description
plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
Version
SOT505-2
plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
plastic extremely thin small outline package; no leads; SOT996-2
8 terminals; body 3 2 0.5 mm
1 page  
NXP Semiconductors
74AHC2G241; 74AHCT2G241
Dual buffer/line driver; 3-state
Table 7. Static characteristics …continued
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions
CI input
capacitance
74AHCT2G241
VIH HIGH-level VCC = 4.5 V to 5.5 V
input voltage
VIL LOW-level VCC = 4.5 V to 5.5 V
input voltage
VOH
VOL
IOZ
II
ICC
ICC
CI
HIGH-level VI = VIH or VIL; VCC = 4.5 V
output voltage IO = 50 A
IO = 8.0 mA
LOW-level VI = VIH or VIL; VCC = 4.5 V
output voltage IO = 50 A
IO = 8.0 mA
OFF-state
VI = VCC or GND;
output current VCC = 5.5 V
input leakage VI = 5.5 V or GND;
current
VCC = 0 V to 5.5 V
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
additional
per input pin; VI = 3.4 V;
supply current other inputs at VCC or GND;
IO = 0 A; VCC = 5.5 V
input
capacitance
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min
Max
- 1.5 10
-
10
-
10 pF
2.0 - - 2.0 - 2.0
-V
- - 0.8 -
0.8
-
0.8 V
4.4 4.5 -
4.4
-
4.4
-V
3.94 - - 3.8 - 3.70 - V
- 0 0.1 -
0.1
-
- - 0.36 - 0.44 -
- - 0.25 -
2.5
-
- - 0.1 -
1.0
-
- - 1.0 -
10
-
- - 1.35 - 1.5 -
0.1 V
0.55 V
10 A
2.0 A
40 A
1.5 mA
- 1.5 10
-
10
-
10 pF
11. Dynamic characteristics
Table 8. Dynamic characteristics
GND = 0 V; for test circuit see Figure 8.
Symbol Parameter Conditions
74AHC2G241
tpd propagation nA to nY; see Figure 5
delay
VCC = 3.0 V to 3.6 V
CL = 15 pF
CL = 50 pF
VCC = 4.5 V to 5.5 V
CL = 15 pF
CL = 50 pF
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
[1]
[2]
- 4.7 8.0 1.0 9.5 1.0 11.5 ns
- 6.6 11.5 1.0
13.0
1.0
14.5 ns
[3]
- 3.4 5.5 1.0
6.5
1.0
7.0 ns
- 4.7 7.5 1.0
8.5
1.0
9.5 ns
74AHC_AHCT2G241
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 13 May 2013
© NXP B.V. 2013. All rights reserved.
5 of 17
5 Page 
NXP Semiconductors
74AHC2G241; 74AHCT2G241
Dual buffer/line driver; 3-state
13. Package outline
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2
D
y
Z
8
5
c
EA
X
HE v M A
pin 1 index
1
e
4
bp w M
A A2
A1
(A3)
detail X
Lp
L
θ
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c D(1) E(1) e
mm
1.1
0.15
0.00
0.95
0.75
0.25
0.38
0.22
0.18
0.08
3.1
2.9
3.1
2.9
0.65
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
HE
4.1
3.9
OUTLINE
VERSION
IEC
REFERENCES
JEDEC
JEITA
SOT505-2
---
L Lp v w y Z(1)
0.5
0.47
0.33
0.2
0.13
0.1
0.70
0.35
θ
8°
0°
EUROPEAN
PROJECTION
ISSUE DATE
02-01-16
Fig 9. Package outline SOT505-2 (TSSOP8)
74AHC_AHCT2G241
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 13 May 2013
© NXP B.V. 2013. All rights reserved.
11 of 17
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