PDF R8A20210BG Data sheet ( Hoja de datos )

Número de pieza	R8A20210BG
Descripción	(R8A20210BG / R8A20211BG) Network Address Search Engine
Fabricantes	Renesas Technology
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No Preview Available ! R8A20211BG/R8A20210BG (MARIE_Blade) Network Address Search Engine (9 M/18 M-bit Full Ternary CAM) REJ03H0001-0100 Rev.1.00 Feb 21, 2005 Description Renesas delivers MARIE_Blade that is a ternary CAM search engine targeted for network packet classifying. The full- custom CAM memory realizes large capacity, high density and low power consumption. www.DataSheet4U.com MARIE_Blade can realize up to 133 Msps in 72-bit/144-bit normal mode (parallel search 266 Msps), 66.5 Msps in 288- bit mode (parallel search 133 Msps) and 33 Msps in 576-bit mode (parallel search 66.5 Msps). The Hierarchical search reduces power consumption; The DX test logic, an extended bit, performs a DX test logic search first (primary search), and the DQ pin performs a DQ array search (secondary search). The parity bit in the DQ array can check for errors as an additional function. Features • 9 M/18 M-bit full ternary CAM • CLK operating frequency 266 MHz Max • Maximum search rate at normal mode: 133 Msps [72-bit/144-bit lookup size] • Maximum search rate at parallel mode: 266 Msps [72-bit/144-bit lookup size] • Maximum search rate at normal mode: 66.5 Msps [288-bit lookup size] • Maximum search rate at parallel mode: 133 Msps [288-bit lookup size] • Maximum search rate at parallel mode: 33 Msps [576-bit lookup size] • Maximum search rate at normal mode: 66.5 Msps [576-bit lookup size] • Priority encoder • Hierarchical search • Parity bit (even parity) check • IEEE 1149.1 test port • 1.2 V core power supply • 1.2 V power supply for search (1.0 V power supply for power saving) • SSTL-2 interface/2.5 V I/O power supply Rev.1.00 Feb 21, 2005 page 1 of 14 1 page R8A20211BG/R8A20210BG (MARIE_Blade) 8. Write Mask Register The Write Mask Register (WMR) controls bits that participate in the Write TCAM operation. The WMR mask has the same bit width as that of corresponding CAM DQ array. Also, this register is valid only during Write TCAM. When writing to the 9 M Mats simultaneously (Greedy Operation), MARIE_Blade uses the mask register that is shared between MAT A and Mat B (Greedy Write). Write Mask 1 01101 www.DataSheet4U.com DQ Write Data DQ Former value DQ DQ Former value DQ TCAM DQ Array The WMR bit width is the same as that of DQ. 1-bit WMR masks 1-bit DQ. Figure 5 Masked Write TCAM 9. Address Source and Data Source A couple of different sources can be selected to write addresses and/or data into the DQ array. Two possible sources for the address input are the DQ input pin and the Address Source Register (ASR). Three possible sources for data input are the DQ input pin, the Data Source Register (DSR), or the Load Data Register (LDR). ⎯ Address Source Register (ASR) There are two sources to input entry addresses to the DQ array: The DQ pin and ASR. An entry address with a hit is stored in the ASR so that the DQ pin can trace hit history with this ASR. In addition, ASR is capable of detecting empty entries as Pseudo Learn. ⎯ Data Source Register (DSR) The DQ input pin, DSR or LDR can be used as a data source. DSR stores data of search miss. Pseudo Learn and Write TCAM to the array can be realized by specifying the DSR having search miss data (data source). Rev.1.00 Feb 21, 2005 page 5 of 14 5 Page R8A20211BG/R8A20210BG (MARIE_Blade) 2. Power/Ground • VCCQ Ball Name A1 A25 C2 C24 E1 E25 Pin Name VCCQ VCCQ VCCQ VCCQ VCCQ VCCQ Ball Name G2 G24 J1 J25 L2 N1 Pin Name VCCQ VCCQ VCCQ VCCQ VCCQ VCCQ Ball Name N25 R2 U1 U25 W2 W24 Pin Name VCCQ VCCQ VCCQ VCCQ VCCQ VCCQ Ball Name AA1 AA25 AC2 AC24 AE1 AE25 Pin Name VCCQ VCCQ VCCQ VCCQ VCCQ VCCQ • V_CORE www.DataSheet4UB.aclol mName Pin Name A3 V_CORE A5 V_CORE A6 V_CORE A7 V_CORE A8 V_CORE A9 V_CORE A10 V_CORE A11 V_CORE A12 V_CORE A13 V_CORE A14 V_CORE A15 V_CORE A16 V_CORE Ball Name A17 A18 A19 A20 A21 D4 D22 E3 E23 F3 F23 K3 T3 Pin Name V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE Ball Name Y3 Y23 AA3 AA23 AB4 AB22 AE3 AE5 AE6 AE7 AE8 AE9 AE10 Pin Name V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE Ball Name AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 Pin Name V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE V_CORE • V_MAT Ball Name D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 Pin Name V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT Ball Name D16 D17 D18 D19 D20 D21 H4 H22 J4 J22 U4 Pin Name V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT Ball Name U22 V4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 Pin Name V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT Ball Name AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 Pin Name V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT V_MAT • VREF Ball Name A4 A22 Pin Name VREF VREF Ball Name L4 N22 Pin Name VREF VREF Ball Name R4 R23 Pin Name VREF VREF Ball Name AE4 AE22 Pin Name VREF VREF Rev.1.00 Feb 21, 2005 page 11 of 14 11 Page

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