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PDF 74LCX16374 Data sheet ( Hoja de datos )
| Número de pieza | 74LCX16374 | |
| Descripción | LOW VOLTAGE CMOS 16-BIT D-TYPE FLIP-FLOP | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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74LCX16374
LOW VOLTAGE CMOS 16-BIT D-TYPE FLIP-FLOP (3-STATE)
WITH 5V TOLERANT INPUTS AND OUTPUTS
s 5V TOLERANT INPUTS AND OUTPUTS
s HIGH SPEED :
fMAX = 150MHz (MIN.) at VCC = 3V
www.DataSheet4U.csomPOWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN) at VCC = 3V
s PCI BUS LEVELS GUARANTEED AT 24 mA
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s OPERATING VOLTAGE RANGE:
VCC(OPR) = 2.0V to 3.6V (1.5V Data
Retention)
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 16374
s LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
s ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTION
The 74LCX16374 is a low voltage CMOS 16 BIT
D-TYPE FLIP-FLOP with 3 STATE OUTPUTS
NON INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C2MOS
technology. It is ideal for low power and high
speed 3.3V applications; it can be interfaced to 5V
signal environment for both inputs and outputs.
These 16 bit D-TYPE flip-flops are controlled by
two clock inputs (nCK) and two output enable in-
puts(nOE). On the positive transition of the (nCK),
the nQ outputs will be set to the logic state that
were setup at the nD inputs. While the (nOE) input
is low, the 8 outputs (nQ) will be in a normal state
(high or low logic level) and while high level the
outputs will be in a high impedance state.
Any output control does not affect the internal op-
eration of flip flops; that is, the old data can be re-
tained or the new data can be entered even while
the outputs are off.
It has same speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
All inputs and outputs are equipped with protec-
tion circuits against static discharge, giving them
2KV ESD immunity and transient excess voltage.
February 2003
TSSOP
ORDER CODES
PACKAGE
TSSOP
TUBE
PIN CONNECTION
T&R
74LCX16374TTR
1/10
1 page  
74LCX16374
AC ELECTRICAL CHARACTERISTICS
Test Condition
Value
Symbol
Parameter
VCC
CL RL ts = tr -40 to 85 °C
-55 to 125 °C Unit
(V) (pF) (Ω) (ns) Min. Max. Min. Max.
tPLH tPHL Propagation Delay
Time
2.7
3.0 to 3.6
50 500 2.5
1.5
1.5
6.5
6.2
1.5
1.5
6.5
6.2
ns
tPZL tPZH Output Enable Time
2.7
1.5 6.3 1.5 6.3
to HIGH and LOW
50 500 2.5
ns
level
3.0 to 3.6
1.5 6.1 1.5 6.1
www.DataSheet4U.cotmPLZ tPHZ Output Disable Time
2.7
1.5 6.2 1.5 6.2
from HIGH and LOW
50 500 2.5
ns
level
3.0 to 3.6
1.5 6.0 1.5 6.0
tS Set-Up Time, HIGH
2.7
2.5 2.5
or LOW level
50 500 2.5
ns
(Dn to CK)
3.0 to 3.6
2.5 2.5
th Hold Time, HIGH or
2.7
1.5 1.5
LOW level
50 500 2.5
ns
(Dn to CK)
3.0 to 3.6
1.5 1.5
tW CK Pulse Width,
HIGH or LOW
2.7
3.0 to 3.6
50 500 2.5
3.0
3.0
3.0
3.0
ns
fMAX
Clock Pulse
Frequency
3.0 to 3.6 50 500 2.5 170
150 MHz
tOSLH
tOSHL
Output To Output
Skew Time (note1,
2)
3.0 to 3.6
50 500 2.5
1.0
1.0 ns
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (tOSLH = | tPLHm - tPLHn|, tOSHL = | tPHLm - tPHLn|)
2) Parameter guaranteed by design
CAPACITIVE CHARACTERISTICS
Test Condition
Value
Symbol
Parameter
VCC
(V)
TA = 25 °C
Min. Typ. Max.
Unit
CIN Input Capacitance
3.3 VIN = 0 to VCC
7 pF
COUT Output Capacitance
3.3 VIN = 0 to VCC
8 pF
CPD Power Dissipation Capacitance
(note 1)
3.3
fIN = 10MHz
VIN = 0 or VCC
20
pF
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/16 (per
circuit)
5/10
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet 74LCX16374.PDF ] | |
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