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PDF KS1453 Data sheet ( Hoja de datos )
| Número de pieza | KS1453 | |
| Descripción | Data Processor | |
| Fabricantes | Samsung Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de KS1453 (archivo pdf) en la parte inferior de esta página. Total 22 Páginas | ||
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DATA PROCESSOR
KS1453
INTRODUCTION
The KS1453 is a Data Process IC which acts as a buffer control for outputting the demodulated data by Hand
Shake. It also executes error corrections of the Sliced output of the RF signal from the disc (EFM signals). It is
compatible with a 1× DVDP/DVD-ROM and a 4× (CLV standard) CD Data Processing. Its other functions include
ECC Error Correction, CD/DVD repeat playback, Descramble, EDC Error Detection, DSI Data Detection, A/V
Decoder Interface, CD/VCD Playback, BCA Decoding, Disc Motor Control, EFM Demodulation and
Synchronization Detection, Protection, Insertion and ID Data Error Correction.
www.DataSheeFt4EUA.coTmURES
• External PLCK input
• EFM/EFM Plus Demodulator
• Sync Protection/Insertion
• CIRC/RS-PC Error Correction (4/16 Erasure Correction)
• Cross/Row Deinterleave
• 4~16 Mbits DRAM Interface (External component for Error Correction/Track Buffer)
• Descramble
• ID Error Correction
• Main Data Error Detection (EDC)
• Error Flag Monitoring
• MICOM Interface
• Micom Direct Memory Access Function (DVD/CD)
• DSI Detection and DSI Data Output
• A/V Decoder Parallel Interface
• Built-in CD-DA Decoder
• Subcode Data Serial Output
• Spindle Servo Control Signal Generation
• DVD Playback
• CD/VCD Playback (1×, 2× 4×)
• BCA Decoding function
• CLV/CAV function
• CD/VCD Repeat Correction Function
• 5 V Single Power Supply
• 128-QFP
• Application Mode: CD_Player, CD_ROM, Video-CD, DVDP Player
1
1 page  
DATA PROCESSOR
No. Pin Name
46 DADR7_OUT
47 DVSS
48 DADR0_OUT
49 DADR6_OUT
50 DADR1_OUT
51 DADR5_OUT
52 DADR2_OUT
53 DADR4_OUT
54 DADR3_OUT
www.DataSheet4U5.c5om DVSS
56 DVSS
57 TOS_OUT
58 DATACK_OUT
59 DVDD
60 SDATA0_OUT
61 SDATA1_OUT
62 SDATA2_OUT
63 SDATA3_OUT
64 SDATA4_OUT
65 SDATA5_OUT
66 SDATA6_OUT
67 SDATA7_BI
68 DVSS
69 CSTROBE_OUT
70 DATREQ_IN
71 DTER_OUT
72 DVSS
73 PWMO7_OUT
74 PWMO6_OUT
75 PWMO5_OUT
76 PWMO4_OUT
77 DVDD
78 PWMO3_OUT
79 PWMO2_OUT
80 PWMO1_OUT
81 PWMO0_OUT
82 DVSS
83 DVSS
84 DVSS
85 DVDD
86 DVDD
87 DVSS
88 DVSS
89 DVSS
90 DVSS
91 FRSYZ_OUT
92 TX_OUT
Description
DRAM Address Bus
Digital GND (0 V)
DRAM Address Bus
DRAM Address Bus
DRAM Address Bus
DRAM Address Bus
DRAM Address Bus
DRAM Address Bus
DRAM Address Bus
Digital GND (0 V)
Digital GND (0 V)
Top of Sector
Data Acknowledge Signal Output
DIGITAL Power (+5 V)
DVD Data/CD Data Bit Stream (CDATA)
DVD Data/CD Data L/R Clock (LRCK)
DVD Data/CD Data Bit Clock (BLCK)
DVD Data/CD Data Error Flag (C2PO)
DVD Data/Subcode Serial Data (SQDT)
DVD Data/Subcode Frame Sync (WFSY)
DVD Data/Subcode Block Sync (S0S1)
DVD Data/Subcode Serial Clock (SQCK)
Digital GND (0 V)
Data Strobe (Clock) Output
Data Request from A/V Decoder or ROM Decoder
DVD Data Error Output
Digital GND (0 V)
PWM Output Signal
PWM Output Signal
PWM Output Signal
PWM Output Signal
Digital Power (+5 V)
PWM Output Signal
PWM Output Signal
PWM Output Signal
PWM Output Signal
Digital GND (0 V)
Digital GND (0 V)
Digital GND (0 V)
DIGITAL Power (+5 V)
DIGITAL Power (+5 V)
Digital GND (0 V)
Digital GND (0 V)
Digital GND (0 V)
Digital GND (0 V)
Frame Sync Out
Digital Out
KS1453
I/O Notes
O DRAM
O DRAM
O DRAM
O DRAM
O DRAM
O DRAM
O DRAM
O DRAM
O AV Decoder
O AV Decoder
O AV Decoder
O AV Decoder
O AV Decoder
O AV Decoder
O AV Decoder
O AV Decoder
O AV Decoder
B AV Decoder
O AV Decoder
I AV Decoder
O AV Decoder
O RF
O RF
O RF
O RF
O RF
O RF
O RF
O RF
O Monitor
O Monitor
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5 Page 
DATA PROCESSOR
KS1453
DRAM
DRAM DATA
DESCRAMBLER
DRAM Cantrol
Signal
Descramble DATA
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Transmission
Transmission
Address Generater Enable Signal
MICOM I/F
MICOM
Setting Valul
EDCFLG
EDC & Built in
DATA
REQ, TOS, ACK, DATCLK
Transmission With CSS
Figure 2. Transmitter Block Diagram
4) CD Audio Feature
- Data with all its errors corrected is input in Bytes, and output serially
- In case of CD - DA, Interpolation, Mute and Attenuation are handled.
5) Subcode I/f Feature
- Serially outputs the Subcode Data (P, Q, R, S, T, V, W) for CD Graphic handling
- Outputs the Subcode Data (Q) for Disc Control after checking for Errors
( p(x) = x16 + x12 + x5 + 1 )
6) BCA Feature
- BCA Code Structure
. 4 RS ECC code max (52, 48) codes/Number of Pure information Bytes - 188 Bytes
. Composed of maximm 208 Bytes. Interleaved in units of 4 Bytes.
. Disc Rotation Speed: 1440 rpm (24 Hz), Channel bit time width - 8.89 us (01 or 10)
- BCA Block Implementation
. Data PLL is designed as an X-tal based clock
. 188 * 8 bits information bits EDC check (32 bits x32 + x31 + x4 + 1 )
. PE RZ mod. [0] → 10, [1] → 01
. BCK Data and Size Detection
. Sync detection (Sync byte, Resync) and Demodulation
. Memory control design for deinterleave and buffering, ECC and EDC
. ECC decoding for 4 (52, 48) codes
11
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet KS1453.PDF ] | |
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