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PDF AT84AS008 Data sheet ( Hoja de datos )

Número de pieza AT84AS008
Descripción 10-Bit 2.2 Gsps ADC
Fabricantes E2V 
Logotipo E2V Logotipo



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Features
10-bit Resolution ADC
2.2 Gsps Sampling Rate
Seamless Ascending Compatibility with TS83102G0B 10-bit 2 Gsps ADC
500 mVpp Full-scale Analog Input Range
100Differential or 50Single-ended Analog input and Clock Input
100Differential Outputs
ECL/LVDS Output Compatibility
Functions:
– ADC Gain Adjust and Sampling Delay Adjust
– Data Ready Output with Asynchronous Reset
– Out-of-range Output Bit
www.DataShPeoetw4Uer.cComonsumption: 4.2W
Power supplies:
– Analog: -5V, 5V
– Digital: -5V to -2.2V and 1.5V
Radiation Tolerant
Package: CBGA152 Cavity Down Hermetic Package
Evaluation Board AT84AS008GL-EB
Companion Device:
– DMUX 10-bit 1:2/1:4 LVDS 2.2 Gsps AT84CS001
Performances
– 3.3 GHz Full Power Input Bandwidth (-3 dB)
– Gain Flatness: ±0.2 dB (from DC up to 1.5 GHz)
– Low Input VSWR: 1.2 Maximum from DC to 2.5 GHz
– Single Tone Performances (-1 dBFs):
SFDR = -58 dBc; 8.0 ENOB; SNR = 52 dBc at FS = 1.7 Gsps, FIN = 850 MHz
SFDR = -54 dBc; 7.6 ENOB; SNR = 50 dBc at FS = 2.2 Gsps, FIN = 1.1 GHz
SFDR = -54 dBc, 7.4 ENOB; SNR = 48 dBc at FS = 2.2 Gsps, FIN = 2 GHz
– Dual Tone Performances (IMD3), Fs = 1.7 Gps, (-7dBFS tone):
(Fin1 = 995 MHz, Fin2 = 1005 MHz): IMD3 = 64 dBFS
(Fin1 = 1545 MHz, Fin2 = 1555 MHz): IMD3 = 62 dBFS
(Fin1 = 1945 MHz, Fin2 = 1955 MHz): IMD3 = 59 dBFS
– Low Bit Error Rate (10-11) at 2.2 Gsps
Screening
– Temperature Range for Packaged Device:
0°C < Tc; Tj < 90°C (Commercial C Grade)
-20°C < Tc; Tj < 110°C (Industrial V Grade)
Applications
– Broadband Direct RF Down Conversion
– Wide Band Satellite Receivers
– Phased Array Antennas, Radars and ECM
– High-speed Instrumentation and High-speed Acquisition Systems
– High Energy Physics
– Automatic Test Equipment
10-bit 2.2 Gsps
ADC
AT84AS008
5404A–BDC–11/06

1 page




AT84AS008 pdf
AT84AS008
3.3 Electrical Characteristics
• VCC = 5V; VEE = DVEE = -5V (unless otherwise specified): ADC performances are independent
of VPLUSD and DVEE common mode voltage and performances are guaranteed in the limit of
the specified VPLUSD range (from -0.9V to 1.7V) and DVEE range (from VEE to -2.1V, as long as
VPLUSD-VEE > 3.5V)
• VIN - VINB = 500 mVpp (full-scale single-ended or differential Input). Clock inputs differential
driven; analog-input single-ended driven
Table 3-3. Electrical Operating Characteristics at Ambient Temperatures and Hot Temperatures
Parameter
Test
Level
Symbol
Min
Typ
Max Unit
Resolution
www.DataSheet4U.com
Power Requirements
10 Bits
Power supply voltage
- analog
- digital (ECL)
- digital (LVDS)
Power supply current
- analog
- digital
ECL
LVDS (DVEE = -2.2)
LVDS (DVEE = -5)
Negative supply voltage
- analog
- digital
Negative supply current
- analog
- digital
ECL
LVDS (DVEE = -2.2)
LVDS (DVEE = -5)
Power dissipation
ECL
LVDS (DVEE = -2.2)
LVDS (DVEE = -5)
Analog Inputs
1 VCC 4.75 5 5.25
1 VPLUSD
-0.8
4 VPLUSD
1.45
V
V
V
1 IVCC
1 IVPLUSD
1 IVPLUSD
1 IVPLUSD
80 100 mA
180 220 mA
160 200 mA
250 300 mA
1 VEE -5.25 -5 -4.75 V
1
DVEE
-5.25
-5
-4.75
V
1 IVEE
1 IDVEE
1 IDVEE
1 IDVEE
620 660 mA
180 220 mA
160 200 mA
250 300 mA
1
1 PD
1
4.2 4.9
4.0 4.8
5.0 5.9
W
W
W
Full-scale input voltage range (differential mode)
(0V common mode voltage)
Full-scale input voltage range (single-ended input
option other input grounded)
Analog input power level (50single-ended)
Analog input capacitance (die)
Input leakage current
Input resistance
- single-ended
- differential
4 VIN, -125
4
VINB
-125
125 mV
125 mV
4
VIN, -250
0
mV
250
4 VINB
mV
4 PIN
-2 dBm
4 CIN 0.3 pF
4 IIN 10 µA
4 RIN 49 50 51
4 RIN 98 100 102
5404A–BDC–11/06
5

5 Page





AT84AS008 arduino
AT84AS008
3.6 Timing Diagram
Figure 3-1.
Timing Diagram
Analog input
External clock
N N+1
TA
Internal clock
Regeneration
www.DataSheet4U.com Latches
Latch 1
Latch 2
Latch 3
Latch 4
Latch 5
Latch 6
Latch 7
Output
Latches
Latch 8
Latch 9
Data ready
N N+1 N+2
N N+1 N+2
N N+1 N+2
N N+1 N+2
N N+1 N+2
Logic encoding
N N+1 N+2
Gray to Binary decoding
N N+1 N+2
Gray to Binary decoding
N N+1 N+2
N N+1 N+2
TDR
Pipeline Delay = 4 clock cycles
TOD TD1 TD2
Outputs
Detailed timing diagram is provided in Section 3.6 on page 11.
3.7 Coding
Table 3-8. ADC Coding Table
Digital Output
Differential
Analog Input
Voltage Level
Binary (B/GB = GND or floating)
MSB………....LSB Out-of-Range
GRAY (B/GB = VEE)
MSB………....LSB Out-of-Range
> + 250.25 mV
>Top end of full-scale + ½ LSB
1111111111
1
1000000000
1
+ 250.25 mV
+ 249.75 mV
Top end of full-scale + ½ LSB
Top end of full-scale - ½ LSB
1111111111
1111111110
0
0
1000000000
1000000001
0
0
+ 125.25 mV
+ 124.75 mV
3/4 full-scale + ½ LSB
3/4 full-scale - ½ LSB
1100000000
1011111111
0
0
1010000000
1110000000
0
0
+ 0.25 mV
-0.25 mV
Midscale + ½ LSB
Midscale - ½ LSB
1000000000
0111111111
0
0
1100000000
0100000000
0
0
-124.75 mV
-124.25 mV
1/4 full-scale + ½ LSB
1/4 full-scale - ½ LSB
0100000000
0011111111
0
0
0110000000
0010000000
0
0
-249.75 mV
-250.25 mV
Bottom end of full-scale + ½ LSB
Bottom end of full-scale - ½ LSB
0000000001
0000000000
0
0
0000000001
0000000000
0
0
< -250.25 mV < Bottom end of full-scale - ½ LSB
0000000000
1
0000000000
1
5404A–BDC–11/06
11

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