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PDF AT17F040A Data sheet ( Hoja de datos )
| Número de pieza | AT17F040A | |
| Descripción | (AT17F040A / AT17F080A) FPGA Configuration Flash Memory | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Prowgwrwam.DmataaSbhleee4t4,1U9.c4o,3m04 x 1 and 8,388,608 x 1-bit Serial Memories Designed to Store
Configuration Programs for Field Programmable Gate Arrays (FPGAs)
• 3.3V Output Capability
• 5V Tolerant I/O Pins
• Program Support using the Atmel ATDH2200E System or Industry Third Party
Programmers
• In-System Programmable (ISP) via 2-wire Bus
• Simple Interface to SRAM FPGAs
• Compatible with Atmel AT40K and AT94K Devices, Altera® FLEX®, Excalibur™, Stratix®,
Cyclone™ and APEX™ Devices
• Cascadable Read-back to Support Additional Configurations or Higher-density Arrays
• Low-power CMOS FLASH Process
• Available in 8-lead LAP, 20-lead PLCC and 32-lead TQFP Packages
• Emulation of Atmel’s AT24CXXX Serial EEPROMs
• Low-power Standby Mode
• Single Device Capable of Holding 4 Bit Stream Files Allowing Simple System
Reconfiguration
• Fast Serial Download Speeds up to 33 MHz
• Endurance: 5,000 Write Cycles Typical
• Green (Lead/Halide-free/ROHS compliant) Packages
FPGA
Configuration
Flash Memory
AT17F040A
AT17F080A
1. Description
The AT17FxxxA Series of In-System Programmable Configuration PROMs (Configu-
rators) provide an easy-to-use, cost-effective configuration memory for Field
Programmable Gate Arrays. The AT17FxxxA Series device is packaged in the 8-lead
LAP, 20-lead PLCC and 32-lead TQFP, see Table 1-1. The AT17FxxxA Series Con-
figurator uses a simple serial-access procedure to configure one or more FPGA
devices.
The AT17FxxxA Series Configurators can be programmed with industry-standard pro-
grammers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable.
Table 1-1. AT17FxxxA Series Packages
Package
AT17F040A
8-lead LAP
Yes
20-lead PLCC
Yes
32-lead TQFP
Yes
AT17F080A
Yes
Yes
Yes
2823D–CNFG–2/08
1 page  
AT17F040A/080A
5.4 PAGESEL[1:0](2)
www.DataSheet4U.com Page select inputs. Used to determine which of the 4 memory pages are targeted during a serial
configuration download. The address space for each of the pages is shown in Table 5-2. When
SER_EN is Low (ISP mode) these pins have no effect.
Table 5-2. Address Space
Paging Decodes
PAGESEL = 00, PAGE_EN = 1
PAGESEL = 01, PAGE_EN = 1
PAGESEL = 10, PAGE_EN = 1
PAGESEL = 11, PAGE_EN = 1
PAGESEL = XX, PAGE_EN = 0
AT17F040A (4 Mbits)
00000 – 0FFFFh
10000 – 1FFFFh
20000 – 2FFFFh
30000 – 3FFFFh
00000 – 3FFFFh
AT17F080A (8 Mbits)
00000 – 1FFFFh
20000 – 3FFFFh
40000 – 5FFFFh
60000 – 7FFFFh
00000 – 7FFFFh
5.5 RESET/OE(1)
Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low level on
RESET/OE resets both the address and bit counters. A High level (with nCS Low) enables the
data output driver.
5.6 nCS(1)
Chip Enable input (active Low). A Low level (with OE High) allows DCLK to increment the
address counter and enables the data output driver. A High level on nCS disables both the
address and bit counters and forces the device into a low-power standby mode. Note that this
pin will not enable/disable the device in the 2-wire Serial Programming mode (SER_EN Low).
5.7 GND
5.8 nCASC
5.9 A2(1)
Ground pin. A 0.2 µF decoupling capacitor between VCC and GND is recommended.
Cascade Select Output (when SER_EN is High). This output goes Low when the internal
address counter has reached its maximum value. If the PAGE_EN input is set High, the maxi-
mum value is the highest address in the selected partition. The PAGESEL[1:0] inputs are used
to make the 4 partition selections. If the PAGE_EN input is set Low, the device is not partitioned
and the address maximum value is the highest address in the device, see Table 5-2 on page 5.
In a daisy chain of AT17FxxxA Series devices, the nCASC pin of one device must be connected
to the nCS input of the next device in the chain. It will stay Low as long as nCS is Low and OE is
High. It will then follow nCS until OE goes Low; thereafter, nCASC will stay High until the entire
EEPROM is read again.
Device selection input, (when SER_EN Low). The input is used to enable (or chip select) the
device during programming (i.e., when SER_EN is Low). Refer to the AT17FxxxA Programming
Specification available on the Atmel web site for additional details.
Notes: 1. This pin has an internal 20 k pull-up resistor.
2. This pin has an internal 30 kΩ pull-down resistor.
2823D–CNFG–2/08
5
5 Page 
AT17F040A/080A
16.1wwwA.DCataCShheeat4rUa.ccotmeristics When Cascading
AT17F040A
AT17F080A
Symbol Description
TCDF(3)
DCLK to Data Float Delay
TOCK(2)
DCLK to nCASC Delay
Commercial
Industrial
Commercial
Industrial
Min Max Min Max
50 50
50 50
50 50
55 55
TOCE(2)
nCS to nCASC Delay
Commercial
Industrial
35 35
40 40
TOOE(2)
RESET/OE to nCASC Delay
Commercial
Industrial
35 35
25 35
Notes: 1. AC test lead = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels.
Units
ns
ns
ns
ns
ns
ns
ns
ns
17. Thermal Resistance Coefficients
Package Type
20J Plastic Leaded Chip Carrier (PLCC)
32A Thin Plastic Quad Flat Package (TQFP)
Note: 1. Airflow = 0 ft/min.
θJC [° C/W]
θJA [° C/W](1)
θJC [° C/W]
θJA [° C/W](1)
AT17F040A
17
62
AT17F080A
–
–
17
62
2823D–CNFG–2/08
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet AT17F040A.PDF ] | |
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