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PDF AT17F32 Data sheet ( Hoja de datos )
| Número de pieza | AT17F32 | |
| Descripción | FPGA Configuration Flash Memory | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Prowgwrwam.DmataaSbhleee3t43U,5.c5o4m,432 x 1-bit Serial Memories Designed to Store Configuration
Programs for Field Programmable Gate Arrays (FPGAs)
• 3.3V Output Capability
• 5V Tolerant I/O Pins
• Program Support using the Atmel ATDH2200E System or Industry Third Party
Programmers
• In-System Programmable (ISP) via 2-wire Bus
• Simple Interface to SRAM FPGAs
• Compatible with Atmel AT40K and AT94K Devices, Altera® FLEX®, APEX™ Devices,
Stratix™, Lattice Semiconductor® (ORCA®) FPGAs, Spartan®, Virtex™ FPGAs
• Cascadable Read-back to Support Additional Configurations or Higher-density Arrays
• Low-power CMOS FLASH Process
• Available in 44-lead PLCC Package
• Emulation of Atmel’s AT24CXXX Serial EEPROMs
• Low-power Standby Mode
• Single Device Capable of Holding 4 Bit Stream Files Allowing Simple System
Reconfiguration
• Fast Serial Download Speeds up to 33 MHz
• Endurance: 10,000 Write Cycles Typical
• LHF Package Available (Lead and Halide Free)
FPGA
Configuration
Flash Memory
AT17F32
1. Description
The AT17F Series of In-System Programmable Configuration PROMs (Configurators)
provide an easy-to-use, cost-effective configuration memory for Field Programmable
Gate Arrays. The AT17F Series device is packaged in the 44-lead PLCC, see Table 1-
1. The AT17F Series Configurator uses a simple serial-access procedure to configure
one or more FPGA devices.
The AT17F Series Configurators can be programmed with industry-standard program-
mers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable.
Table 1-1. AT17F Series Packages
Package
44-lead PLCC
AT17F32
Yes
3393C–CNFG–6/05
1 page  
AT17F32
5.4 PAGESEL[1:0](2)
www.DataSheet4U.com Page select inputs. Used to determine which of the 4 memory pages are targeted during a serial
configuration download. The address space for each of the pages is shown in Table 5-2. When
SER_EN is Low (ISP mode) these pins have no effect.
Table 5-2. Address Space
Paging Decodes
PAGESEL = 00, PAGE_EN = 1
PAGESEL = 01, PAGE_EN = 1
PAGESEL = 10, PAGE_EN = 1
PAGESEL = 11, PAGE_EN = 1
PAGESEL = XX, PAGE_EN = 0
AT17F32 (32 Mbits)
000000 – 07FFFFh
080000 – 0FFFFFh
100000 – 17FFFFh
180000 – 1FFFFFh
000000 – 1FFFFFh
5.5 RESET/OE(1)
Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low level on
RESET/OE resets both the address and bit counters. A High level (with CE Low) enables the
data output driver.
5.6 CE(1)
Chip Enable input (active Low). A Low level (with OE High) allows CLK to increment the address
counter and enables the data output driver. A High level on CE disables both the address and bit
counters and forces the device into a low-power standby mode. Note that this pin will not
enable/disable the device in the 2-wire Serial Programming mode (SER_EN Low).
5.7 GND
5.8 CEO
5.9 A2(1)
Ground pin. A 0.2 µF decoupling capacitor between VCC and GND is recommended.
Chip Enable Output (when SER_EN is High). This output goes Low when the internal address
counter has reached its maximum value. If the PAGE_EN input is set High, the maximum value
is the highest address in the selected partition. The PAGESEL[1:0] inputs are used to make the
4 partition selections. If the PAGE_EN input is set Low, the device is not partitioned and the
address maximum value is the highest address in the device, see Table 5-2 on page 5. In a
daisy chain of AT17F Series devices, the CEO pin of one device must be connected to the CE
input of the next device in the chain. It will stay Low as long as CE is Low and OE is High. It will
then follow CE until OE goes Low; thereafter, CEO will stay High until the entire EEPROM is
read again.
Device selection input, (when SER_EN Low). The input is used to enable (or chip select) the
device during programming (i.e., when SER_EN is Low). Refer to the AT17F Programming
Specification available on the Atmel web site (www.atmel.com) for additional details.
Notes: 1. This pin has an internal 20 KΩ pull-up resistor.
2. This pin has an internal 30 KΩ pull-down resistor.
3393C–CNFG–6/05
5
5 Page 
AT17F32
16.1wwwA.DCataCShheeat4rUa.ccotmeristics When Cascading
AT17F32
Symbol
Description
Min Max Units
TCDF(3)
CLK to Data Float Delay
Commercial
Industrial
50 ns
50 ns
TOCK(2)
CLK to CEO Delay
Commercial
Industrial
50 ns
55 ns
TOCE(2)
CE to CEO Delay
Commercial
Industrial
35 ns
40 ns
TOOE(2)
RESET/OE to CEO Delay
Commercial
Industrial
35
35
Notes: 1. AC test lead = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels.
ns
ns
17. Thermal Resistance Coefficients
Package Type
44J Plastic Leaded Chip Carrier (PLCC)
Note: 1. Airflow = 0 ft/min.
θJC [°C/W]
θJA [°C/W](1)
AT17F32
15
50
3393C–CNFG–6/05
11
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| PDF Descargar | [ Datasheet AT17F32.PDF ] | |
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