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PDF AT49SN12804 Data sheet ( Hoja de datos )
| Número de pieza | AT49SN12804 | |
| Descripción | 128-megabit (8M x 16) Burst/Page Mode 1.8-volt Flash Memory | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• 1.6w5wVw-.D1.a9ta5SVhReeeta4dU/.Wcormite
• High Performance
– Random Access Time – 70 ns
– Page Mode Read Time – 20 ns
– Synchronous Burst Frequency – 66 MHz
– Configurable Burst Operation
• Sector Erase Architecture
– Sixteen 4K Word Sectors with Individual Write Lockout
– Two Hundred Fifty-four 32K Word Main Sectors with Individual Write Lockout
• Typical Sector Erase Time: 32K Word Sectors – 500 ms; 4K Word Sectors – 100 ms
• Thirty-two Plane Organization, Permitting Concurrent Read in Any of the Thirty-one
Planes not Being Programmed/Erased
• Suspend/Resume Feature for Erase and Program
– Supports Reading and Programming Data from Any Sector by Suspending Erase
of a Different Sector
– Supports Reading Any Word by Suspending Programming of Any Other Word
• Low-power Operation
– 30 mA Active
– 10 µA Standby
• VPP Pin for Write Protection and Accelerated Program/Erase Operations
• RESET Input for Device Initialization
• CBGA and TSOP Packages
• Seventeen 128-bit Protection Registers (2,176 Bits)
• Common Flash Interface (CFI)
Description
The AT49SN/SV12804 is a 1.8-volt 128-megabit Flash memory. The memory is
divided into multiple sectors and planes for erase operations. The AT49SN/SV12804
is organized as 8,388,608 x 16 bits. The device can be read or reprogrammed off a
single 1.8V power supply, making it ideally suited for In-System programming. The
device can be configured to operate in the asynchronous/page read (default mode) or
burst read mode (not available for the AT49SV12804). The burst read mode is used to
achieve a faster data rate than is possible in the asynchronous/page read mode. If the
AVD and the CLK signals are both tied to GND and the burst configuration register is
configured to perform asynchronous reads, the device will behave like a standard
asynchronous Flash memory. In the page mode, the AVD signal can be tied to GND or
can be pulsed low to latch the page address. In both cases the CLK can be tied to
GND.
The AT49SN/SV12804 is divided into thirty-two memory planes. A read operation can
occur in any of the thirty-one planes which is not being programmed or erased. This
concurrent operation allows improved system performance by not requiring the sys-
tem to wait for a program or erase operation to complete before a read is performed.
To further increase the flexibility of the device, it contains an Erase Suspend and Pro-
gram Suspend feature. This feature will put the erase or program on hold for any
amount of time and let the user read data from or program data to any of the remain-
ing sectors. There is no reason to suspend the erase or program operation if the data
to be read is in another memory plane.
The VPP pin provides data protection and faster programming and erase times. When
the VPP input is below 0.4V, the program and erase functions are inhibited. When VPP
is at 0.9V or above, normal program and erase operations can be performed. With VPP
at 12.0V, the program (Dual-word Program command) and erase operations are
accelerated.
128-megabit
(8M x 16)
Burst/Page
Mode 1.8-volt
Flash Memory
AT49SN12804
AT49SV12804
Preliminary
Rev. 3314A–FLASH–4/04
1
1 page  
AT49SN/SV12804 [Preliminary]
www.DataSheet4U.com
FIXED-LENGTH BURST READS: During a fixed-length burst mode read, four, eight or six-
teen words of data may be burst from the device, depending upon the configuration. The
device supports a linear burst mode. The burst sequence is shown on page 21. When operat-
ing in the linear burst read mode (B7 = 1) with the burst wrap bit (B3 = 1) set, the device may
incur an output delay when the burst sequence crosses the first 16-word boundary in the
memory. If the starting is D0 - D12, there is no delay. If the starting address is D13 - D15, an
output delay equal to the initial clock latency is incurred. The delay takes place only once, and
only if the burst sequence crosses a 16-word boundary. To indicate that the device is not
ready to continue the burst, the device will drive the WAIT pin low (B10 and B8 = 0) during the
clock cycles in which new data is not being presented. Once the WAIT pin is driven high (B10
and B8 = 0), the current data will be valid. The WAIT signal will be tri-stated when the CE or
OE signal is high.
The “Four-word Burst Read Waveform” on page 32 illustrates a fixed-length burst cycle. The
valid address is latched at point A. For the specified clock latency of four, data D0 is valid
within 13 ns of clock edge B. The low-to-high transition of the clock at point C results in D1
being read. Similarly, D2 and D3 are output following the next two clock cycles. Returning CE
high ends the read cycle. There is no output delay in the burst access wrap mode (B3 = 0).
BURST SUSPEND: The Burst Suspend feature allows the system to temporarily suspend a
synchronous burst operation if the system needs to use the Flash address and data bus for
other purposes. Burst accesses can be suspended during the initial latency (before data is
received) or after the device has output data. When a burst access is suspended, internal
array sensing continues and any previously latched internal data is retained.
Burst Suspend occurs when CE is asserted, the current address has been latched (either ris-
ing edge of AVD or valid CLK edge), CLK is halted, and OE is deasserted. The CLK can be
halted when it is at VIH or VIL. To resume the burst access, OE is reasserted and the CLK is
restarted. Subsequent CLK edges resume the burst sequence where it left off.
Within the device, OE gates the WAIT signal. Therefore, during Burst Suspend the WAIT sig-
nal reverts to a high-impedance state when OE is deasserted. See “Burst Suspend Waveform”
on page 32.
RESET: A RESET input pin is provided to ease some system applications. When RESET is at
a logic high level, the device is in its standard operating mode. A low level on the RESET pin
halts the present device operation and puts the outputs of the device in a high-impedance
state. When a high level is reasserted on the RESET pin, the device returns to read mode.
ERASE: Before a word can be reprogrammed it must be erased. The erased state of the
memory bits is a logical “1”. The entire memory can be erased by using the Chip Erase com-
mand or individual planes can be erased by using the Plane Erase command or individual
sectors can be erased by using the Sector Erase command.
3314A–FLASH–4/04
5
5 Page 
AT49SN/SV12804 [Preliminary]
www.DataSheet4U.com
ERASE SUSPEND/ERASE RESUME: The Erase Suspend command allows the system to
interrupt a sector erase or plane erase operation. The erase suspend command does not work
with the Chip Erase feature. Using the erase suspend command to suspend a sector erase
operation, the system can program or read data from a different sector within the same plane.
Since this device is organized into thirty-two planes, there is no need to use the erase suspend
feature while erasing a sector when you want to read data from a sector in another plane. After
the Erase Suspend command is given, the device requires a maximum time of 15 µs to sus-
pend the erase operation. After the erase operation has been suspended, the plane that
contains the suspended sector enters the erase-suspend-read mode. The system can then
read data or program data to any other sector within the device. An address is not required
during the Erase Suspend command. During a sector erase suspend, another sector cannot
be erased. To resume the sector erase operation, the system must write the Erase Resume
command. The Erase Resume command is a one-bus cycle command, which does require
the plane address. Read, Read Status Register, Product ID Entry, Clear Status Register, Pro-
gram, Program Suspend, Erase Resume, Sector Softlock/Hardlock, Sector Unlock are valid
commands during an erase suspend.
PROGRAM SUSPEND/PROGRAM RESUME: The Program Suspend command allows the
system to interrupt a programming operation and then read data from a different word within
the memory. After the Program Suspend command is given, the device requires a maximum
of 10 µs to suspend the programming operation. After the programming operation has been
suspended, the system can then read from any other word within the device. An address is not
required during the program suspend operation. To resume the programming operation, the
system must write the Program Resume command. The program suspend and resume are
one-bus cycle commands. The command sequence for the erase suspend and program sus-
pend are the same, and the command sequence for the erase resume and program resume
are the same. Read, Read Status Register, Product ID Entry, Program Resume are valid com-
mands during a Program Suspend.
128-BIT PROTECTION REGISTERS: The AT49SN/SV12804 contains seventeen (PR0 -
PR16) 128-bit registers that can be used for security purposes in system design. Please see
the Protection Register Addressing Table on page 19 for the address locations within each
protection register. The first protection register (PR0) is divided into two 64-bit blocks. The two
blocks are designated as block A and block B. The data in block A is non-changeable and is
programmed at the factory with a unique number. The data in block B is programmed by the
user and can be locked out such that data in the block cannot be reprogrammed. The other 16
registers (PR1 - PR16) have 128 bits (16 words) each that are all user programmable. To pro-
gram block B in PR0 or to program PR1 - PR16 register, a two-bus cycle command must be
used as shown in the Command Definition table on page 18. To lock out block B in PRO or to
lock out PR1 - PR16, a two-bus cycle command must also be used as shown in the Command
Definition table. To lock out block B in PRO, the address used in the second bus cycle is 080h
and data bit D1 must be zero during the second bus cycle. All other data bits during the sec-
ond bus cycle are don’t cares. To lock out PR1 - PR16, the address used in the second bus
cycle is 089h and sixteen bits of data are programmed. If any of these bits is programmed to a
zero, the appropriate register is locked. After being locked, the protection register cannot be
unlocked. To determine whether block B in PRO or PR1 - PR16 is locked out, the Product ID
Entry command is given followed by a read operation from address 80H or address 89H,
respectively. (This command is shown as status of protection in the Command Definition
table). For block B in PRO, if data bit D1 is zero, block B is locked. If data bit D1 is one, block B
can be reprogrammed. For PR1 - PR16, sixteen bits of data are read out. Each bit represents
the protection status of a particular register. If the bit is a zero, the register is locked. If the bit
is a one, the register can be reprogrammed. To read a protection register, the Product ID Entry
command is given followed by a normal read operation from an address within the protection
register. After determining whether a register is protected or not or reading the protection reg-
ister, the Read command must be given to return to the read mode.
3314A–FLASH–4/04
11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AT49SN12804.PDF ] | |
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