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PDF AT49SV163D Data sheet ( Hoja de datos )
| Número de pieza | AT49SV163D | |
| Descripción | 16-megabit 1M x 16) 1.8-volt Only Flash Memory | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Sinwgwlew.VDoalttaaSgheeeRt4eUa.dc/oWmrite Operation: 1.65V to 1.95V
• Access Time – 80 ns
• Sector Erase Architecture
– Thirty-one 32K Word (64K Bytes) Sectors with Individual Write Lockout
– Eight 4K Word (8K Bytes) Sectors with Individual Write Lockout
• Fast Word Program Time – 10 µs
• Fast Sector Erase Time – 100 ms
• Suspend/Resume Feature for Erase and Program
– Supports Reading and Programming from Any Sector by Suspending Erase
of a Different Sector
– Supports Reading Any Word in the Non-suspending Sectors by Suspending
Programming of Any Other Word
• Low-power Operation
– 10 mA Active
– 15 µA Standby
• Data Polling, Toggle Bit, Ready/Busy for End of Program Detection
• VPP Pin for Write Protection and Accelerated Program Operation
• RESET Input for Device Initialization
• Sector Lockdown Support
• TSOP and CBGA Package Options
• Top or Bottom Boot Block Configuration Available
• 128-bit Protection Register
• Minimum 100,000 Erase Cycles
• Common Flash Interface (CFI)
16-megabit
(1M x 16)
1.8-volt Only
Flash Memory
AT49SV163D
AT49SV163DT
1. Description
The AT49SV163D(T) is a 1.8-volt 16-megabit Flash memory organized as 1,048,576
words of 16 bits each. The memory is divided into 39 sectors for erase operations.
The device is offered in a 48-lead TSOP and a 48-ball CBGA package. The device
has CE and OE control signals to avoid any bus contention. This device can be read
or reprogrammed using a single power supply, making it ideally suited for in-system
programming.
The device powers on in the read mode. Command sequences are used to place the
device in other operation modes such as program and erase. The device has the
capability to protect the data in any sector (see “Sector Lockdown” on page 6).
To increase the flexibility of the device, it contains an Erase Suspend and Program
Suspend feature. This feature will put the erase or program on hold for any amount of
time and let the user read data from or program data to any of the remaining sectors
within the memory. The end of a program or an erase cycle is detected by the
READY/BUSY pin, Data Polling or by the toggle bit.
The VPP pin provides data protection. When the VPP input is below 0.4V, the program
and erase functions are inhibited. When VPP is at 1.65V or above, normal program
and erase operations can be performed. With VPP at 10.0V, the program (Dual-word
Program command) operation is accelerated.
3656A–FLASH–2/07
1 page  
AT49SV163D(T)
4.6 VPP Pin
www.DataSheet4U.com
The circuitry of the AT49SV163D(T) is designed so that the device cannot be programmed or
erased if the VPP voltage is less that 0.4V. When VPP is at 1.65V or above, normal program
and erase operations can be performed. The VPP pin cannot be left floating.
4.7 Program/Erase Status
The device provides several bits to determine the status of a program or erase operation: I/O2,
I/O3, I/O5, I/O6 and I/O7. The “Status Bit Table” on page 11 and the following four sections
describe the function of these bits. To provide greater flexibility for system designers, the
AT49SV163D(T) contains a programmable configuration register. The configuration register
allows the user to specify the status bit operation. The configuration register can be set to one
of two different values, “00” or “01”. If the configuration register is set to “00”, the part will auto-
matically return to the read mode after a successful program or erase operation. If the
configuration register is set to a “01”, a Product ID Exit command must be given after a suc-
cessful program or erase operation before the part will return to the read mode. It is important
to note that whether the configuration register is set to a “00” or to a “01”, any unsuccessful
program or erase operation requires using the Product ID Exit command to return the device
to read mode. The default value (after power-up) for the configuration register is “00”. Using
the four-bus cycle Set Configuration Register command as shown in the “Command Definition
Table” on page 12, the value of the configuration register can be changed. Voltages applied to
the RESET pin will not alter the value of the configuration register. The value of the configura-
tion register will affect the operation of the I/O7 status bit as described below.
4.7.1
Data Polling
The AT49SV163D(T) features Data Polling to indicate the end of a program cycle. If the status
configuration register is set to a “00”, during a program cycle an attempted read of the last
word loaded will result in the complement of the loaded data on I/O7. Once the program cycle
has been completed, true data is valid on all outputs and the next cycle may begin. During a
chip or sector erase operation, an attempt to read the device will give a “0” on I/O7. Once the
program or erase cycle has completed, true data will be read from the device. Data Polling
may begin at any time during the program cycle. Please see “Status Bit Table” on page 11 for
more details.
If the status bit configuration register is set to a “01”, the I/O7 status bit will be low while the
device is actively programming or erasing data. I/O7 will go high when the device has com-
pleted a program or erase operation. Once I/O7 has gone high, status information on the other
pins can be checked.
The Data Polling status bit must be used in conjunction with the erase/program and VPP status
bit as shown in the algorithm in Figures 4-1 and 4-2 on page 9.
4.7.2 Toggle Bit
In addition to Data Polling the AT49SV163D(T) provides another method for determining the
end of a program or erase cycle. During a program or erase operation, successive attempts to
read data from the memory will result in I/O6 toggling between one and zero. Once the pro-
gram cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the
toggle bit may begin at any time during a program cycle. Please see “Status Bit Table” on
page 11 for more details.
The toggle bit status bit should be used in conjunction with the erase/program and VPP status
bit as shown in the algorithm in Figures 4-3 and 4-3 on page 10.
3656A–FLASH–2/07
5
5 Page 
AT49SV163D(T)
5. Status Bit Table
www.DataSheet4U.com
Status Bit
I/O7
I/O7
I/O6
I/O5(1)
I/O3(2)
I/O2 RDY/BUSY
Configuration Register
00
01
00/01
00/01
00/01
00/01
00/01
Programming
I/O7 0 TOGGLE 0 0 1 0
Erasing
0 0 TOGGLE 0 0 TOGGLE 0
Erase Suspended & Read
Erasing Sector
1
1
1
0
0 TOGGLE 1
Erase Suspended & Read
Non-erasing Sector
DATA
DATA
DATA
DATA
DATA
DATA
1
Erase Suspended &
Program Non-erasing Sector
I/O7
0 TOGGLE 0
0 TOGGLE 0
Erase Suspended &
Program Suspended and
Reading from Non-
suspended Sectors
DATA
DATA
DATA
DATA
DATA
DATA
1
Program Suspended & Read
Programming Sector
I/O7
1
1
0
0 TOGGLE 1
Program Suspended & Read
Non-programming Sector
DATA
DATA
DATA
DATA
DATA
DATA
1
Notes: 1. I/O5 switches to a “1” when a program or an erase operation has exceeded the maximum time limits or when a program or
sector erase operation is performed on a protected sector.
2. I/O3 switches to a “1” when the VPP level is not high enough to successfully perform program and erase operations.
3656A–FLASH–2/07
11
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