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PDF AT7911E Data sheet ( Hoja de datos )
| Número de pieza | AT7911E | |
| Descripción | Triple SpaceWire links High Speed Controller | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Alswowwk.nDoatwaSnheaest4SUM.coCmS332SpW
• 3 identical bidirectional SpaceWire links allowing
– full duplex communication
– transmit rate from 1.25 up to 200 Mbit/s in each direction
• Derived from the TSS901E-SMCS332 triple IEEE 1355 high speed controller
– Known anomalies of the TSS901E chip corrected
– Slightly different startup behavior
• COmmunication Memory Interface (COMI)
– autonomous accesses to a communication memory
• HOst Control Interface (HOCI)
– gives read/write accesses to the AT7911E configuration registers
– gives read/write accesses to the SpaceWire channels
• Arbitration unit
– Allows two AT7911E to share one Dual Port RAM without external arbitration
• Scalable databus width
– 8/16/32 bit width available
– allows flexible integration with any CPU type
• Allows Little endian and Big endian configuration
• Performance
– At 3.3V: 100 Mbit/s full duplex communication in each direction
– At 5V: 200 Mbit/s full duplex communication in each direction
• Operating range
– Voltages
• 3V to 3.6V
• 4.5V to 5.5V
– Temperature
• - 55°C to +125°C
• Maximum Power consumption
– At 3.6V with a 15MHz clock : 0.4 W
– At 5.5V with a 25 MHz clock : 1.7 W
• Radiation Performance
– Total dose tested successfully up to 50 Krad (Si)
– No single event latchup below a LET of 80 MeV/mg/cm2
• ESD better than 2000V
• Quality Grades :
– QML-Q or V with SMD
• Package : 196 pins MQFPL
• Mass : 12grams
Triple
SpaceWire links
High Speed
Controller
AT7911E
1 page  
AT7911E
3. Pin Description
www.DataSheet4U.com Table 2. Pin description
Signal Name(1)(3) Type(2)(4)
Function
HSEL*
HRD*
HWR*
HADR(7:0)
HDATA(31:0)
HACK
HINTR*
SMCSADR(3:0 )
SMCSID(3:0)
HOSTBIGE
BOOTLINK
CMCS(1:0)*
CMRD*
CMWR*
CMADR(15:0)
CMDATA(31:0)
COCI
COCO
CAM
CPUR*
SES(3:0)*
LDI1
LSI1
LDO1
I Select host interface
I host interface read strobe
I host interface write strobe
I
AT7911E register address lines. These address lines will be
used to access (address) the AT7911E registers.
IO/Z AT7911E data
host acknowledge. The AT7911E deasserts this output to
O/Z add waitstates to an AT7911E access. After AT7911E is
ready this output will be asserted.
O/Z host interrupt request line
I
Address. The binary value of these lines will be compared
with the value of the ID lines.
I
ID lines: offers possibility to use sixteen AT7911E within one
HSEL*
0: host I/F Little Endian
I
1: host I/F Big Endian
0: control by host
I
1: control by link
Communication memory select lines. These pins are
O/Z asserted as chip selects for the corresponding banks of the
communication memory.
O/Z
Communication memory read strobe. This pin is asserted
when the AT7911E reads data from memory.
O/Z
Communication memory write strobe. This pin is asserted
when the AT7911E writes to data memory.
O/Z
Communication memory address. The AT7911E outputs an
address on these pins.
IOZ
Communication memory data. The AT7911E inputs and
outputs data from and to com. memory on these pins.
I Communication interface 'occupied' input signal
O Communication interface 'occupied' output signal
Communication interface arbitration master input signal
I 1: master
0: slave
O CPU Reset Signal (can be used as user defined flag)
O Specific External Signals (can be used as user defined flags)
I Link Data Input channel 1
I Link Strobe Input channel 1
O Link Data Output channel 1
5V ± 0.5V
max. output
current [mA]
3
3
3
6
6
6
6
3
3
3
3
12
3.3V ± 0.3V
max. output
current [mA]
load [pF]
1.5 50
1.5 50
1.5 50
3 25
3 25
3 25
3 25
1.5 25
1.5 50
1.5 50
1.5 50
6 25
7737B–AERO–05/08
5
5 Page 
AT7911E
6. Operating Modes
www.DataSheet4U.com According to the different protocol formats expected for the operation of the AT7911E, two major
operation modes are implemented into the AT7911E. For each link channel the operation modes
are chosen individually by setting the respective configuration registers via the HOCI or via the
link.
6.1 Simple Interprocessor Communication (SIC) Protocol Mode
This mode executes the simple interprocessor communication protocol as described in the
chapter 13 of the 'SMCS332SpW User Manual'.
The following capabilities of the protocol are implemented into the AT7911E:
• Interpretation of the first 4 data characters as the header bytes of the protocol
• Autonomous execution of the simple control commands as described in the above mentioned
chapter
• Autonomous acknowledgement of received packets if configured
In transmit direction no interpretation of the data is performed. This means that for transmit pack-
ets, the four header bytes must be generated by the host CPU and must be available as the first
data read from the communication memory. EOP control characters are automatically inserted
by the AT7911E when one configured transfer from the communication memory has finished.
6.2 Transparent Mode (default after reset)
This mode allows complete transparent data transfer between two nodes without performing any
interpretation of the databytes and without generating any acknowledges. It is completely up to
the host CPU to interpret the received data and to generate acknowledges if required.
The AT7911E accepts EOP and EEP control tokens as packet delimiters and generates autono-
mously EOP or no EOP (as configured) marker after each end of a transmission packet.
The transparent mode includes as a special submode: Wormhole routing.
6.2.1
Wormhole routing
This mode allows hardware routing of packets by the AT7911E. It is a submode of the transpar-
ent mode. The AT7911E introduces a wormhole routing function similar to the routing
implemented in the SpaceWire router. Each of the three links and the AT7911E itself can be
assigned an eight bit address. When routing is enabled in the AT7911E, the first byte of a packet
will be interpreted as the address destination byte, analysed and removed from the packet
(header deletion). If this address matches one of the two other link addresses or the AT7911E
address assigned previously, the packet will be automatically forwarded to this link or the FIFO
of the AT7911E. If the header byte does not match a link address, the packet will be written to
the internal FIFO as well and an error interrupt (maskable) will be raised.
7. Fault Tolerance
The SpaceWire standard specifies low level checks as link disconnect, credit value, sequence
and parity at token level. The AT7911E provides, through the Protocol Processing Unit, features
7737B–AERO–05/08
11
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet AT7911E.PDF ] | |
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