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PDF ATF280E Data sheet ( Hoja de datos )
| Número de pieza | ATF280E | |
| Descripción | Rad Hard Reprogrammable FPGA | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• SRwAwMwb.DaastaeSdhFePetG4UA.cdoemsigned for Space use
– 280K equivalent ASIC gates
– Unlimited reprogrammability
– SEE hardened cells (Configuration RAM, FreeRAMTM, DFF, JTAG, I/O buffers)
– No need for Triple Modular Redundancy (TMR)
• FreeRAM™:
– 115200 Bits of Distributed RAM
– 32x4 RAM blocks organization
– Independent of Logic Cells
– Single/Dual Port capability
– Synchronous/Asynchronous capability
• Global Reset Option
• 8 Global Clocks and 4 Fast Clocks
• 8 LVDS transceivers and 8 LVDS receivers
• Cold sparing and PCI Compliant I/Os
– 308 for 472pins MCGA package
– 150 for 256pins MQFPF package
• Flexible Configuration modes
– Master/Slave Capability
– Serial/Parallel Capability
– Check of the data during FPGA configuration
• Self Integrity Check (SIC) of the configuration during FPGA operation
• Performance
– 100 MHz Internal Performance
– 50MHz System Performance
– 10ns 32X4 FreeRAM™ access time
• Operating range
– Voltages
• 1.65V to 1.95V (Core)
• 3V to 3.6V (Clustered I/Os)
– Temperature
• - 55°C to +125°C
• Radiation Performance
– Total Dose tested up to 300 krads (Si)
– No single event latch-up below a LET of 80 MeV/mg/cm2
• ESD better than 2000V
• Quality Grades
– QML-Q or V
– ESCC
• Ceramic packages
– 256pins MQFPF (150 I/Os, 8 LVDS Tx and 8 LVDS Rx)
– 472pins MCGA (308 I/Os, 8 LVDS Tx and 8 LVDS Rx)
• Design Kit including
– ATF280E and Configurator Samples
– Evaluation Board
– Software Design Tools
– ISP Cable/Dongle
Rad Hard
Reprogrammable
FPGA
ATF280E
Advance
Information
7750A–AERO–07/07
1 page  
Table 2-2.
LEwwAwD.DataSheeSt4igUn.caolm
Cluster
G7 IO 12
G8 VCC 12
G9 IO/D1 12
G10 IO
12
G11 VCC
12
G12 IO
10
G13 IO
10
G14 IO
10
G15 IO
10
G16 IO
9
G17 IO/GCK4
9
G18 IO/D10
9
G19 IO
9
G20 IO
9
G21 IO
9
G22 IO
9
H1 IO/A4
1
H2 IO
1
H3 IO
1
H4 IO
1
H5 VCC
1
H6 IO
1
H7 IO
1
H8 VCC
1
H9 VCC 12
H10 IO
12
H11 IO
12
H12 IO
12
H13 IO
10
H14 VCC
10
H15 VCC
10
H16 VCC
9
H17 IO
9
H18 IO
9
H19 IO
9
H20 IO
9
H21 IO
9
H22 IO
9
ATF280E MCGA472 pin assignment
LEAD
J8
J9
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
L1
Signal
VCC
IO
IO
IO
IO
IO
IO/GCK5
VCC
IO
IO
IO
VCC
IO/D11
IO
IO
IO
ILVDS8
ILVDS7
VCC
IO
VCC
IO
IO
IO
TCK
IO
IO
RESETN
IO
IO
VCC
IO
VCC
IO
OLVDS4N
OLVDS3N
IO
IO/A7
Cluster
1
1
12
12
12
10
10
9
9
9
9
9
9
9
9
1
2
2
1
1
1
1
1
1
1
12
10
10
9
9
9
9
9
9
8
8
9
1
LEAD
L9
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
N1
N2
ATF280E
Signal
IO
IO/A6
IO
IO
IO
IO
VCC
IO
IO
IO
IO
OLVDS4
OLVDS3
IO
IO
OLVDS7
OLVDS8
VCCB
IO
IO
IO
IO
IO
IO
IO
IO/D14
IO
IO/D12
VCCB
IO/D13
IO
REFSouth
VCC
ILVDS3N
ILVDS4N
IO
IO
OLVDS7N
Cluster
3
1
1
10
9
9
9
9
9
9
9
8
8
7
1
2
2
2
3
3
3
3
3
3
4
7
7
9
8
7
7
8
7
8
8
7
3
2
7750A–AERO–07/07
5
5 Page 
ATF280E
www.DataSheet4U.com
INIT is a multi-function pin. During power-on-reset and manual reset, the pin functions as an
open drain bi-directional I/O which releases High when the configuration clear cycle is complete,
but can be held Low to hold the configuration in a reset state. Once released, the FPGA will pro-
ceed to either configuration download or idle, as appropriate. During configuration download, the
INIT pin is again an open drain bi-directional pin which signals if an error is encountered during
the download of a configuration bitstream. In addition, during the Check Function, the INIT pin
drives Low for any configuration SRAM mismatch (see the description of the Check Function on
page 16 for more details). While in open drain mode, the pin is pulled to VDD with a nominal 20K
internal resistor. When not configuring, the INIT pin becomes a fully functional user I/O.
CON - Configuration Status (Input/Output)
CON is the FPGA configuration start and status pin. It is a dedicated open drain bi-directional
pin. During power-on-reset or manual reset, CON is driven Low by the FPGA. In Modes 2, 6, or
7, when the FPGA has finished the configuration clear cycle, CON is released to indicate the
device is ready for the user to initiate configuration download. The user may then drive CON
Low to initiate a configuration download. After three clock cycles, CON is then driven Low by the
FPGA until it finishes the download, and it is then released. In Mode 0, CON is not released by
the FPGA at the end of power-on-reset or manual reset. Instead, CON is controlled by the FPGA
until the end of the auto-configuration process. CON is released at the end of configuration
download in Mode 0, and the user may then initiate a manual configuration download by driving
CON Low. While in open drain mode, the pin is pulled to VDD with a nominal 10K internal
resistor.
HDC - High During Configuration (output)
HDC(1) is driven High by the FPGA during power-on-reset, manual reset, and configuration
download. During normal operation, the pin is a fully functional user I/O.
Note: 1. All user I/O default to inputs with pull-ups “on”. The HDC pin transitions from driving a
strong “1” to a pull-up “1” after reset. The HDC pin will transition from driving a strong “1” to the
user programmed state at the end of configuration download. If not programmed, the default
state is input with pull-up.
LDC - Low During Configuration (output)
HDC(1) is driven Low by the FPGA during power-on-reset, manual reset, and configuration
download. During normal operation, the pin is a fully functional user I/O.
Note: 1. All user I/O default to inputs with pull-ups “on”. The HDC pin transitions from driving a
strong “1” to a pull-up “1” after reset. The HDC pin will transition from driving a strong “1” to the
user programmed state at the end of configuration download. If not programmed, the default
state is input with pull-up.
D0 - Configuration Data Bus - LSB (Input/Output)
D0 is the lsb of the FPGA configuration data bus used to download configuration data to the
device. During power-on-reset or manual reset, D0 is controlled by the configuration SRAM. The
D0 pin will transition from the user programmed state to a CMOS input with a nominal 20K inter-
nal pull-up resistor as the SRAM at that location is cleared by the configuration clear cycle. D0
becomes an input during configuration download.
D1:D15 - Configuration Data Bus - Upper bits (Input/Output)
D1:D15 are the upper bits of the 8/16-bit parallel data bus used to download configuration data
to the device. During power-on-reset or manual reset, D1:D15 are controlled by the configura-
7750A–AERO–07/07
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ATF280E.PDF ] | |
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