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PDF ATSAM3703 Data sheet ( Hoja de datos )

Número de pieza ATSAM3703
Descripción Audio Processing
Fabricantes ATMEL Corporation 
Logotipo ATMEL Corporation Logotipo



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No Preview Available ! ATSAM3703 Hoja de datos, Descripción, Manual

Features
ThrwewewD.DSaPtasSahneedt42U4.-cboimt Audio Router On-chip
32 kHz to 96 kHz Sampling Rate
Enhanced P16 Processor with C Compiler
New 48-bit Double-precision DSP Instructions
Built-in 16K x 16 Flash Memory
Built-in 8K x 24 RAM
Secure Code - Copy Protected
Direct Connection of LEDs, Switches
Direct Connection of LCD Display
8 Channels for Audio In + Out
DDR-SDRAM/SDRAM Support in Burst Mode
MIDI In/Out
8-bit Parallel Interface
Warm Start Power-down
Deep Power-down (< 5 µA) Using Built-in Power Switch
LQFP80 Package
Typical Applications: Effect Processing (reverb, echo, chorus, etc.), MP3 Decoding,
Filtering, Sampling Rate Conversion, Professional Audio, Consumer Electronic, MP3
Player
1. Description
The ATSAM3703 is a new member of the SAM3000 family of sound synthesis/pro-
cessing ICs that uses the DSP array technology. It is designed for superior quality
sound processing. The 16-bit processor has new instructions and a C compiler for
quicker reliable firmware development. Total compatibility is maintained with the other
members of the family. Applications written for the ATSAM3703 can be burned into
the built-in Flash memory. This memory has specific features to avoid external read of
the coded data, thus ensuring very effective copy protection.
The minimum configuration for a product is ATSAM3703 + Codec. An external
SDRAM/DDR-SDRAM is needed if the 8K internal RAM is not sufficient for extended
delay line buffers, such as high-quality reverb.
Audio
Processing
ATSAM3703
High-
performance
Low-cost
Effect
Processor
6237A–DRMSD–29-May-06

1 page




ATSAM3703 pdf
ATSAM3703
4. Typical Application Examples
www.DataSheet4U.com
4.1 Low Cost, High Quality Effect
Figure 4-1.
Switches,
LCD Display
MIDI
ATSAM3703
ADC
DAC
Stereo Audio In/Out
• High quality, full 24-bit multi-effects like reverb, chorus, compressor, etc.
• Stereo 10-band graphic equalizer
4.2 Host-controlled MP3 Player
Figure 4-2.
Copmpressed
Audio
(from host)
ATSAM3703
DAC
Stereo Audio Out
• ATSAM3703 firmware download from host (when using parallel interface)
• Choice of host communication interfaces:
– 8-bit parallel
– Asynchronous serial
– Synchronous serial (SPI
• Full MP3 support including very low bit rates extension (ISO/IEC 13818-3).
• Easily upgradable to other coding standards
4.3 Toys with “Artificial Intelligence”
Figure 4-3.
Switches,
Motor
Control
ATSAM3703
ADC
DAC
Audio In/Out
• Speech recognition
• Learning functions
• ADPCM record / play
6237A–DRMSD–29-May-06
5

5 Page





ATSAM3703 arduino
ATSAM3703
Table 6-1. ATSAM3703 Pin Description (Continued)
Pin wNwawm.DeataSheet4PUi.ncoNmumber
Type
Sharing
X1 - X2
64, 63
--
RESET
14
STIN
STOUT
65
79
PDWN
60
TEST
15
In -
In
-
Pd
Out -
In -
In
-
Pd
Description
External crystal connection. Standard frequencies are 6.9552
MHz, 9.6 MHz, 11.2896 MHz, 12.288 MHz. Max frequency is
12.5 MHz. An external clock (max. 1.8Vpp) can be connected
to X1 using AC coupling (22pF). A built-in PLL multiplies the
clock frequency by 4 for internal use.
Master reset Schmitt trigger input, active low. RESET should
be held low during at least 10ms after power is applied. On the
rising edge of RESET, the chip enters an initialization routine,
which may involve firmware download from an external
SmartMedia, or host.
Serial test input. This is a 57.6 kbauds asynchronous input
used for firmware debugging. This pin is tested at power-up.
The built-in debugger starts if STIN is found high. STIN has a
built-in pull-down. It should be grounded or left open for normal
operation.
Serial test output. 57.6 kbauds async output used for firmware
debugging.
Power down input, active low. High level on this pin is typ.
VC18. When PDWN is low, the oscillator and PLL are stopped,
the power switch opens, and the chip enters a deep sleep
mode (1µA typ. consumption when power switch is used). To
exit from power down, PDWN has to be set high then RESET
applied. Alternate programmable power-downs are available
which allow warm restart of the chip.
Test input. Should be grounded or left open.
6237A–DRMSD–29-May-06
11

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