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PDF 6805E2E Data sheet ( Hoja de datos )
| Número de pieza | 6805E2E | |
| Descripción | CDP6805E2E | |
| Fabricantes | InnovASIC | |
| Logotipo |  |
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IA6805E2
Microprocessor Unit
Data Sheet
As of Production Version 00
FEATURESwww.DataSheet4U.com
• Form, Fit, and Function Compatible with the Harris© CDP6805E2CE and
Motorola© MC146805E2
• Internal 8-bit Timer with 7-Bit
Programmable Prescaler
• On-chip Clock
• Memory Mapped I/O
• Versatile Interrupt Handling
• True Bit Manipulation
• Bit Test and Branch Instruction
• Vectored Interrupts
• Power-saving STOP and WAIT Modes
• Fully Static Operation
• 112 Bytes of RAM
The IA6805E2 is a "plug-and-play" drop-in replacement for the original IC. innovASIC produces
replacement ICs using its MILESTM, or Managed IC Lifetime Extension System, cloning technology. This
technology produces replacement ICs far more complex than "emulation" while ensuring they are compatible
with the original IC. MILESTM captures the design of a clone so it can be produced even as silicon
technology advances. MILESTM also verifies the clone against the original IC so that even the
"undocumented features" are duplicated. This data sheet documents all necessary engineering information
about the IA6805E2 including functional and I/O descriptions, electrical characteristics, and applicable
timing.
Package Pinout
RESET_N
IRQ_N
LI
DS
RW_N
AS
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
A12
A11
A10
A9
A8
VSS
(1)
IA6805E2
(2)
40 Pin DIP
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(40)
(39)
(38)
(37)
(36)
(35)
(34)
(33)
(32)
(31)
(30)
(29)
(28)
(27)
(26)
(25)
(24)
(23)
(22)
(21)
VDD
OSC1
OSC2
TIMER
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
B0
B1
B2
B3
B4
B5
B6
B7
AS
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
NC
NC
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
IA6805E2
44 Pin LCC
(39) PB1
(38) PB2
(37) PB3
(36) PB4
(35) PB5
(34) PB6
(33) PB7
(32) B0
(31) B1
(30) B2
(29) B3
Copyright © 2002
innovASIC
The End of Obsolescence™
ENG21108140100
Page 1 of 31
www.innovasic.com
Customer Support:
1-888-824-4184
1 page  
IA6805E2
Microprocessor Unit
Data Sheet
As of Production Version 00
Crystal Parameters Representative Frequencies:
www.DataSheet4U.com
RS max
C0
C1
Q
COSC1
COSC2
5.0 MHz 4.0 MHz 1.0 MHz
50Ω 75Ω 400Ω
8 pF 7 pF 5 pF
0.02 pF 0.012 pF 0.008 pF
50 k 40 k 30 k
15-30 pF 15-30 pF 15-40 pF
15-25 pF 15-25 pF 15-30 pF
Oscillator Connections:
38
OSC2
38
OSC2
CRYSTAL CIRCUIT
L
C1 RS
39
C0
OSC1
39
OSC1
CRYSTAL OSCILLATOR CONNECTIONS
ia6805E2
10 MΩ
38 39
OSC2
C OSC2
OSC1
C OSC1
OSC1
39
OSC2
NC 38
IA6805E2
OSC1 PIN
tOL
t
tOLOL
tOH
Figure 3. OSC1, OSC2 (System Clock)
OSC1 to Bus Transitions Timing Waveforms:
OSC1
AS
DS
RW_n
A[12:8]
B[7:0]
MPU READ
MUX ADDR
MPU
READ
DATA*
B[7:0]
MPU WRITE
MUX ADDR
MPU WRITE DATA
*READ DATA "LATCHED" ON DS FALL
Figure 4. OSC1, OSC2 (System Clock)
Copyright © 2002
innovASIC
The End of Obsolescence™
ENG21108140100
Page 5 of 31
www.innovasic.com
Customer Support:
1-888-824-4184
5 Page 
IA6805E2
Microprocessor Unit
Data Sheet
As of Production Version 00
wwwE.DxattaeSrhneaetl4IUn.ctoemrrupt:
If the external interrupt pin irq_n is “low” and the interrupt mask bit of the condition code
register is cleared, the external interrupt occurs. When the interrupt is recognized, the
current state of the machine is pushed onto the stack and the condition code register I-bit
gets set masking further interrupts until the present one is serviced. The program counter is
then loaded with the contents of the interrupt vector, which contains the location of the
interrupt service routine. The contents of $1FFA and $1FFB specify the address for this
service routine. A functional diagram of the external interrupt is shown in Figure 9 and a
mode diagram of the external interrupt is shown in Figure 10. The timing diagram shows
two different treatments of the interrupt line (irq_n) to the processor. The first shows
several interrupt lines “wire ORed” to form the interrupts at the processor. If the interrupt
line (irq_n) remains low after servicing an interrupt, the next interrupt is recognized. The
second shows single pulses on the interrupt line spaced far enough apart to be serviced. The
minimum time between pulses is a function of the length of the interrupt service. After a
pulse occurs, the next pulse should not occur until an RTI has occurred. The time between
pulses (tILIL) is obtained by adding 20 instruction cycles to the total number of cycles it takes
to complete the service routine including the RTI instruction.
INTERRUPT PIN
VDD
DQ
C
Q
R
EXTERNAL
INTERUPT
REQUEST
I BIT (CCR)
POWER-ON RESET
EXTERNAL RESET
EXTERNAL INTERRUPT
BEING SERVICED
Figure 9. Interrupt Functional Diagram
Copyright © 2002
innovASIC
The End of Obsolescence™
ENG21108140100
Page 11 of 31
www.innovasic.com
Customer Support:
1-888-824-4184
11 Page | ||
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