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PDF YGV629 Data sheet ( Hoja de datos )
| Número de pieza | YGV629 | |
| Descripción | VC1 Video Controller 1 | |
| Fabricantes | YAMAHA CORPORATION | |
| Logotipo |  |
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YGV629
VC1
Video Controller 1
■ Outline
YGV629 (Function name: VC1, hereinafter described as VC1) is a VDP (Video Display Processor), which
has a pattern rendering function by the sprite method according to the attribute settings and a direct line
rendering function. Since various effect functions are included sufficiently in the sprite function and line
rendering function, more effective presentation can be realized.
Since VC1 can display the bit map image with free display resolution, NTSC to SVGA, on any screen size
of monitor, OSD display control for various display units can be made.
And, VC1 includes a line buffer as a VRAM, so the system can be built with a little part. In addition,
pattern memory can be connected directly, so that the amount of the control program can be reduced.
■ Features
□Display Function
Pattern rendering by the sprite method according to the attribute settings, and OSD display by the direct
line rendering according to the attribute settings.
Two display layers: Sprite display layer and Line display layer, up to 341 can be displayed.
However, for the line display layer, up to 1 layer can be displayed.
Alpha-blending function between layers.
□Sprite Plane Function
Sprite display of the field on the screen, up to 341
Size 8×8 to 512×512 dots, independent selection (horizontal & vertical) possible. (in 8 dots)
2, 16, 32, 64, or 256 palette colors in 64k colors, 64k-color natural picture display by 16-bit RGB
Reverse function in right to left or up and down
Scaling function
Alpha-blending function in pixels
Anti-aliasing function at the outline part
YGV629 CATALOG
CATALOG No.: LSI-4GV629A50
2006.05
1 page  
YGV629
■ Pin Tablewww.DataSheet4U.com
Pin Name No. I/O
Function
Level 5Tr Drive
CPU Interface
D7-0
8 I/O CPU Data Bus
LVCMOS ○ 4mA
PS2-0
3 I CPU Port Selection
LVCMOS ○
CS_N
1 I Chip Select
LVCMOS ○
RD_N
1 I Read Pulse
LVCMOS ○
WR_N
1 I Write Pulse
LVCMOS ○
WAIT_N
1 OT CPU Bus Wait
LVCMOS ○ 4mA
READY_N 1 OT CPU Bus Ready
LVCMOS ○ 4mA
INT_N
1 Od Interrupt
LVCMOS ○ 4mA
SER_N
1 I CPU Interface Selection
LVCMOS ○
SCS_N
1 I Serial Interface Chip Select
LVCMOS ○
SDIN
1 I Serial Interface Data Input
LVCMOS ○
SDOUT
1 OT Serial Interface Data Output
LVCMOS ○ 4mA
SCLK
1 I Serial Clock Input
LVCMOS ○
RESET_N
1 I Reset
LVCMOS ○
Pattern Memory Interface
MD15-0
16 I/O Pattern Memory Data Bus
LVCMOS ○ 4mA
MA24-0
25 OT Pattern Memory Address Bus
LVCMOS ○ 4mA
MOE_N
1 OT Pattern Memory Output Enable
LVCMOS ○ 4mA
MWE_N
1 OT Pattern Memory Write Pulse
LVCMOS ○ 4mA
RAHZ_N
1 I Pattern Memory High Impedance Switching
LVCMOS ○
Monitor Interface
R,G,B
3 O Analog Image Output
Analog
IREF
1 - DAC Reference Power Supply
Analog
DR5-0
6 O Digital Image R Output
LVCMOS
4mA
DG5-0
6 O Digital Image G Output
LVCMOS
4mA
DB5-0
6 O Digital Image B Output
LVCMOS
4mA
VSYNC_N 1 O Vertical Synchronizing Signal Output
LVCMOS
4mA
HCSYNC_N
1
O
Horizontal Synchronizing / Composite
Synchronizing Signal Output
LVCMOS
4mA
VSIN_N
1 I Vertical Synchronizing Input
LVCMOS ○
HSIN_N
1 I Horizontal Synchronizing Input
LVCMOS ○
BLANK_N 1 O Display Timing Output
LVCMOS
4mA
FSC 1 O Sub-carrier Clock
LVCMOS
4mA
YS_N
1 O YS Output
LVCMOS
4mA
DOTCLK
1 O Dot Clock Output
LVCMOS
4mA
Clock
XIN 1 I Reference Clock Input
XOUT
1 O X’tal connection pin
DTCKIN
1 I Display system Clock Input
LVCMOS ○
DTCKS_N
1 I Display system Clock Selection
LVCMOS ○
FILTER
1 - PLL Filter Connection
Analog
PLLCTL5-0 6 I PLL Control
LVCMOS ○
Od: open drain output, OT: 3-state output, 5Tr: 5V Tolerant, Drive: driving capability
Note) VC1 has no built-in pull up resistor. Pull up the pins externally as necessary.
The tolerant attribute is an attribute of the input buffer, output buffer that can become the high-impedance
state, and bi-directional buffer, and indicates it can endure the 5V signal.
-5- 4GV629A50
5 Page 
YGV629
wzww.DWatAaSIhTe_etN4U(.3co-smtate output Pin No.23)
CPU bus wait pin. The bus wait request signal to CPU is output from this pin when using in 8-bit parallel
interface.
z READY_N (3-state output Pin No.24)
CPU bus ready pin. The bus ready signal to CPU is output from this pin when using in 8-bit parallel
interface.
z INT_N (Open drain output Pin No.25)
Interrupt signal output pin. An interrupt request signal to CPU is output.
z SER_N (Output Pin No.38)
CPU interface selection pin.
This pin selects which to select as a CPU interface from the serial interface or the 8-bit parallel interface.
z SCS_N(Input Pin No.36)
Serial interface chip select input pin.
The chip-select signal is input when using in the serial interface. SDIN pin and SCLK pin becomes valid
z SDIN (Input Pin No.35)
Serial data input pin.
Data is input when using in serial interface.
z SDOUT (3-state output Pin No.34)
Serial data output pin. Data is output when using in serial interface.
z SCLK (Input Pin No.37)
Serial clock input pin. A clock is input when using in serial interface.
■ Pattern Memory Interface
Each pin of the pattern memory interface is used as the interface with the pattern memory, which is connected
to the VC1 local bus. Mask-ROM, NOR type flash-memory, and SRAM, etc. can be connected to the pattern
memory.
z MD15-0 (Input Output Pin No.75-80, 83-90, 93, 94)
Pattern memory data bus pin. These pins are connected to the data bus of the pattern memory.
z MA24 - 0(3-state output Pin No.42-47, 49-54, 57-62, 64-70)
Pattern memory address bus pin. These pins are connected to the address bus of the pattern memory.
z MOE_N(3-state output Pin No.74)
Pattern memory output enable pin. The output enable signal to the pattern memory is output.
z MWE_N(3-state output Pin No.73)
Pattern memory write pulse output pin. The write enable signal to the pattern memory is output.
z RAHZ_N (Input Pin No.95)
Pattern memory high-impedance switching pin.
-11-
4GV629A50
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet YGV629.PDF ] | |
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