PDF WED3DL3216V Data sheet ( Hoja de datos )

Número de pieza	WED3DL3216V
Descripción	16Mx32 SDRAM
Fabricantes	White Electronic Designs
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No Preview Available ! www.datasheet4u.com White Electronic Designs WED3DL3216V 16Mx32 SDRAM FEATURES 40% Space Savings vs. Monolithic Solution Reduced System Inductance and Capacitance 3.3V Operating Supply Voltage Fully Synchronous to Positive Clock Edge Clock Frequencies of 100MHz - 133MHz Burst Operation • Sequential or Interleave • Burst Length = Programmable 1, 2, 4, 8 or Full Page • Burst Read and Write • Multiple Burst Read and Single Write Data Mask Control Per Byte Auto and Self Refresh Automatic and Controlled Precharge Commands Suspend Mode and Power Down Mode 119 Pin BGA, 17mm x 23mm DESCRIPTION The WED3DL3216V is an 16Mx32 Synchronous DRAM conﬁgured as 4x4Mx32. The SDRAM BGA is constructed with two 16Mx16 SDRAM die mounted on a multi-layer laminate substrate and packaged in a 119 lead, 17mm by 23mm, BGA. The WED3DL3216V is available in clock speeds of 133MHz, 125MHz, and 100MHz. The range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. The package and design provides performance enhancements via a 50% reduction in capacitance vs. two monolithic devices. The design includes internal ground and power planes which reduces inductance on the ground and power pins allowing for improved decoupling and a reduction in system noise. PIN CONFIGURATION (Top view) 123 4 5 67 A VCCQ NC B NC NC BA0 NC A10 A12 CAS# A11 A7 VCCQ A NC NC B C NC NC BA1 VCC A9 A8 NC C D DQC NC VSS NC VSS NC DQB D E DQC DQC VSS CE# VSS DQB DQB E F VCCQ DQC VSS RAS# VSS DQB VCCQ F G DQC DQC DQMC NC DQMB DQB DQB G H DQC DQC VSS CKE VSS DQB DQB H J VCCQ VCC NC VCC NC VCC VCCQ J K DQD DQD VSS CK VSS DQA DQA K L DQD DQD DQMD NC DQMA DQA DQA L M VCCQ DQD VSS WE# VSS DQA VCCQ M N DQD DQD VSS A1 VSS DQA DQA N P DQD NC VSS A0 VSS NC DQA P R NC A6 NC VCC NC A2 NC R T NC NC A5 A4 A3 NC NC T U VCCQ NC NC NC NC NC VCCQ U 123 4 5 67 PIN DESCRIPTION A0 – A12 Address Bus BA0-1 Bank Select Addresses DQ Data Bus CK Clock CKE Clock Enable DQM Data Input/Output Mask RAS# Row Address Strobe CAS# Column Address Strobe CE# Chip Enable VCC Power Supply pins, 3.3V VCCQ Data Bus Power Supply pins,3.3V VSS Ground pins White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice. January, 2004 Rev. 0 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 1 page www.datasheet4u.com White Electronic Designs WED3DL3216V Parameter Clock to valid Output delay1,2 Output Data Hold Time2 Clock HIGH Pulse Width3 Clock LOW Pulse Width3 Input Setup Time3 Input Hold Time3 CK to Output Low-Z2 CK to Output High-Z Row Active to Row Active Delay4 RAS to CAS Delay4 Row Precharge Time4 Row Active Time4 Row Cycle Time - Operation4 Row Cycle Time - Auto Refresh4,8 Last Data in to New Column Address Delay5 Last Data in to Row Precharge5 Last Data in to Burst Stop5 Column Address to Column Address Delay6 Number of Valid OutputData7 SDRAM AC CHARACTERISTICS CL = 3 CL = 2 Symbol tCC tCC tSAC tOH tCH tCL tSS tSH tSLZ tSHZ tRRD tRCD tRP tRAS tRC tRFC tCDL tRDL tBDL tCCD 133MHZ Min Max 7 1000 7.5 1000 5.4 3 2.5 2.5 1.5 0.8 2 5.4 24 24 24 60 10,000 90 90 1 1 1 1.5 2 1 125MHZ Min Max 8 1000 10 1000 6 3 3 3 2 1 2 6 20 20 20 50 10,000 70 70 1 1 1 1.5 2 1 100MHZ Min Max 10 1000 12 1000 7 3 3 3 2 1 2 7 20 20 20 50 10,000 80 80 1 1 1 1.5 2 2 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CK CK CK CK ea NOTES: 1. Parameters depend on programmed CAS latency. 2. If clock rise time is longer than 1ns (tRISE/2 -0.5)ns should be added to the parameter. 3. Assumed input rise and fall time = 1ns. If tRISE or tFALL are longer than 1ns. [(tRISE = tFALL)/2] - 1ns should be added to the parameter. 4. The minimum number of clock cycles required is detemined by dividing the minimum time required by the clock cycle time and then rounding up to the next higher integer. 5. Minimum delay is required to complete write. 6. All devices allow every cycle column address changes. 7. In case of row precharge interrupt, auto precharge and read burst stop. White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice. January, 2004 Rev. 0 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 5 Page www.datasheet4u.com White Electronic Designs WED3DL3216V MODE REGISTER DEFINITION A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus Reserved* WB Op Mode CAS Latency BT Burst Length Mode Register (Mx) *Program M12, M11, M10 = "0, 0, 0" to ensure compatibility with future devices. M2 M1 M0 000 001 010 011 100 101 110 111 Burst Length M3 = 0 1 2 4 8 Reserved Reserved Reserved Full Page M3 = 1 1 2 4 8 Reserved Reserved Reserved Reserved M3 Burst Type 0 Sequential 1 Interleaved M6 M5 M4 000 001 010 011 100 101 110 111 CAS Latency Reserved Reserved 2 3 Reserved Reserved Reserved Reserved M8 M7 M6-M0 Operating Mode 0 0 Defined Standard Operation -- - All other states reserved M9 Write Burst Mode 0 Programmed Burst Length 1 Single Location Access White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice. January, 2004 Rev. 0 11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 11 Page

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