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PDF ATL25 Data sheet ( Hoja de datos )
| Número de pieza | ATL25 | |
| Descripción | ASIC | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ATL25 (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
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Features
• Available in Gate Array or Embedded Array
• High-speed, 100 ps Gate Delay, 2-input NAND, FO = 2 (nominal)
• Up to 6.9 Million Used Gates and 976 Pins
• 0.25µ Geometry in up to Five-level Metal
• System-level Integration Technology
www.da–taCshoereets4u: .AcoRmM7TDMI™, ARM920T™, ARM946E-S™ and MIPS64™ 5Kf™ RISC
Microprocessors; AVR® RISC Microcontroller; OakDSPCore™, Teak™ and
PalmDSPCore™ Digital Signal Processors; 10/100 Ethernet MAC, USB, 1394, 1284,
CAN and Other Assorted Processor Peripherals
– Analog Functions: DACs, ADCs, OPAMPs, Comparators, PLLs and PORs
– Soft Macro Memory: Gate Array
SRAM — ROM — DPSRAM — FIFO
– Hard Macro Memory: Embedded Array
SRAM — ROM — DPSRAM — FIFO — Stacked E2 — Stacked Flash
– I/O Interfaces: CMOS, LVTTL, LVDS, PCI, USB; Output Currents up to 16 mA
@2.5V; 2.5V Native I/O, 3.3V Tolerant/Compliant I/O, 5.0V Tolerant I/O
Description
The ATL25 Series ASIC family is fabricated on a 0.25µ CMOS process with up to five
levels of metal. This family features arrays with up to 6.9 million routable gates and
976 pins. The high density and high pin count capabilities of the ATL25 family, coupled
with the ability to add embedded microprocessor cores, DSP engines and memory on
the same silicon, make the ATL25 series of ASICs an ideal choice for system-level
integration.
Figure 1. ATL25 Gate Array ASIC
ASIC
ATL25 Series
Standard
Gate Array
Architecture
Figure 2. ATL25 Embedded Array ASIC
Standard
Gate Array
Architecture
Analog
1414C–ASIC-08/02
1
1 page  
ATL25 Series ASIC
Pin Definition
Requirements
The corner pads are reserved for power and ground only. All other pads are fully programma-
ble as input, output, bidirectional, power, or ground. When implementing a design with 3.3V
compliant buffers, an appropriate number of pad sites must be reserved for the VDD 3 pins,
which are used to distribute 3.3V power to the compliant buffers.
wwDw.edastaisghenet4Ou.cpomtions
Logic Synthesis
ASIC Design
Translation
FPGA and PLD
Conversions
Atmel can accept RTL designs in Verilog or VHDL HDL formats. Atmel fully supports Synop-
sys for Verilog or VHDL simulation as well as synthesis. Of the two HDL formats, Verilog and
VHDL, Atmel’s preferred HDL format for ASIC design is Verilog.
Atmel has successfully translated existing designs from most major ASIC vendors into Atmel
ASICs. These designs have been optimized for speed and gate count and modified to add
logic or memory, or replicated as a pin-for-pin compatible, drop-in replacement.
Atmel has successfully translated existing FPGA/PLD designs from most major vendors into
Atmel ASICs. There are four primary reasons to convert from an FPGA/PLD to an ASIC:
• Conversion of high-volume devices for a single or combined design is cost effective.
• Performance can often be optimized for speed or low power consumption.
• Several FPGA/PLDs can be combined onto a single chip to minimize cost while reducing
on-board space requirements.
• In situations where an FPGA/PLD was used for fast cycle time prototyping, an ASIC may
provide a lower cost answer for long-term volume production.
1414C–ASIC-08/02
5
5 Page 
ATL25 Series ASIC
Table 5. 3.3-volt DC Characteristics
Applicable over recommended operating temperature and voltage range unless otherwise noted.
Symbol Parameter
Buffer
Test Condition
Min Typ
TA
Operating
Temperature
www.datasheet4u.com
VDD Supply Voltage
All
All Except 3.3V
Compliant I/O
−55
2.3 2.5
VDD3
IIH
IIL
Supply Voltage
High-level Input
Current
Low-level Input
Current
3.3V Compliant I/O
CMOS
CMOS
VIN = VDD,
VDD = VDD (max)
VIN = VSS,
VDD = VDD (max)
Pull-up = 620 KΩ
3.0 3.3
−10
High-impedance
IOZ State Output
Current
All
VIN = VDD or VSS
VDD = VDD (max)
No pull-up
−10
2 mA Buffer
IOS
Output Short-circuit
Current
2 mA Buffer
VOUT = VDD,
VDD = VDD (max)
VOUT = VSS,
VDD = VDD (max)
CMOS, LVTTL
10
−9
2.0
VIH
High-level Input
Voltage
PCI
CMOS/TTL-level
Schmitt
0.475VDD3
2.0
1.7
CMOS
VIL
Low-level Input
Voltage
PCI
CMOS/TTL-level
Schmitt
1.1
VHYS
VOH
Hysteresis
High-level Output
Voltage
TTL-level Schmitt
PO11
PCI
VOL
Note:
Low-level Output
Voltage
PO11
PCI
All I/Os 3.3V Tolerant/Compliant
IOH = 2 mA,
VDD3 = VDD (min)
IOH = 500 µA
IOL = 2 mA,
VDD3 = VDD (min)
IOL = 1.5 mA
0.8VDD3
0.9VDD3
0.6
Max
125
2.7
3.6
10
Units
°C
V
V
µA
µA
10 µA
mA
V
0.8
0.325VDD3
0.8
V
V
V
0.2VDD
0.1VDD
V
1414C–ASIC-08/02
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet ATL25.PDF ] | |
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