PDF ZL30112 Data sheet ( Hoja de datos )

Número de pieza	ZL30112
Descripción	SLIC/CODEC DPLL
Fabricantes	Zarlink Semiconductor
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No Preview Available ! ZL30112 SLIC/CODEC DPLL Data Sheet Features • Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or www.datas1he9e.4t44u.cMomHz input • Provides 2.048 MHz and 8.192 MHz output clocks and an 8 kHz framing pulse • Automatic entry and exit from freerun mode on reference fail • Provides DPLL lock and reference fail indication • DPLL bandwidth of 29 Hz for all rates of input references • Less than 0.6 nsecpp intrinsic jitter on all output clocks • 20 MHz external master clock source: clock oscillator or crystal • Simple hardware control interface November 2007 Ordering Information ZL30112LDE1 32 Pin QFN* Tubes, Bake & Drypack *Pb Free Matte Tin -40°C to +85°C Applications • Synchronizer for POTS SLIC/CODEC • Rate convert NTR 8 kHz or GPON physical interface clock to TDM clock Description The ZL30112 SLIC/CODEC DPLL contains a digital phase-locked loop (DPLL), which provides timing and synchronization for SLIC/CODEC devices. The ZL30112 generates TDM clock and framing signals that are phase locked to the input reference. It helps ensure system reliability by monitoring its reference for stability and by maintaining stable output clocks during short periods when the reference is unavailable. REF RST OSCi OSCo Reference Monitor State Machine Master Clock REF_FAIL LOCK DPLL Mode Control C2o C8o F8ko Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2007, Zarlink Semiconductor Inc. All Rights Reserved. 1 page ZL30112 Data Sheet 3.0 Functional Description The ZL30112 is a SLIC/CODEC DPLL providing timing (clock) and synchronization (frame) signals to network interface cards. Figure 1 is a functional block diagram which is described in the following sections. 3.1 Reference Monitor www.datasheet4u.com The input reference is monitored by two reference monitor blocks. The block diagram of reference monitoring is shown in Figure 3. The reference frequency is detected and the clock is continuously monitored for two independent criteria that indicate abnormal behavior of the reference signal, for example; loss of clock or excessive level of frequency error. To ensure proper operation of the reference monitor circuit, the minimum input pulse width restriction of 15 nsec must be observed. • Reference Frequency Detector (RFD): This detector determines whether the frequency of the reference clock is 8 kHz, 2.048 MHz, 8.192 MHz or 19.44 MHz and provides this information to the various monitor circuits and the phase detector circuit of the DPLL. • Coarse Frequency Monitor (CFM): This circuit monitors the reference frequency over intervals of approximately 30 µs to quickly detect large frequency changes. • Single Cycle Monitor (SCM): This detector checks the period of a single clock cycle to detect large phase hits or the complete loss of the clock. REF Reference Frequency Detector Coarse Frequency Monitor Single Cycle Monitor OR REF_FAIL Mode select state machine DPLL in FreeRun Mode Figure 3 - Reference Monitor Circuit Exceeding the thresholds of any of the monitors forces the corresponding REF_FAIL pin to go high. The single cycle and coarse frequency failure flags force the DPLL into FreeRun mode. 5 Zarlink Semiconductor Inc. 5 Page ZL30112 Data Sheet The output clock should be connected directly (not AC coupled) to the OSCi input of the ZL30112 and the OSCo output should be left open as shown in Figure 6. www.datasheet4u.com ZL30112 OSCi +3.3 V +3.3 V 20 MHz OUT GND 0.1 µF OSCo No Connection Figure 6 - Clock Oscillator Circuit 6.2.2 Crystal Oscillator Alternatively, a Crystal Oscillator may be used. A complete oscillator circuit made up of a crystal, resistor and capacitors is shown in Figure 7. The accuracy of a crystal oscillator depends on the crystal tolerance as well as the load capacitance tolerance. Typically, for a 20 MHz crystal specified with a 32 pF load capacitance, each 1 pF change in load capacitance contributes approximately 9 ppm to the frequency deviation. Consequently, capacitor tolerances and stray capacitances have a major effect on the accuracy of the oscillator frequency. The crystal should be a fundamental mode type - not an overtone. The fundamental mode crystal permits a simpler oscillator circuit with no additional filter components and is less likely to generate spurious responses. The crystal specification is as follows. 1 Frequency 20 MHz 2 Tolerance As required 3 Oscillation Mode Fundamental 4 Resonance Mode Parallel 5 Load Capacitance As required 6 Maximum Series Resistance 50 Ω Table 2 - Typical Crystal Oscillator Specification 11 Zarlink Semiconductor Inc. 11 Page

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