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PDF ATtiny43U Data sheet ( Hoja de datos )
| Número de pieza | ATtiny43U | |
| Descripción | Microcontroller | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• High Performance, Low Power AVR® 8-bit Microcontroller
• Advanced RISC Architecture
– 123 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
• Non-volatile Program and Data Memories
– 4K Bytes of In-System Programmable Program Memory Flash
– 64 Bytes of In-System Programmable EEPROM
– 256 Bytes of Internal SRAM
– Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM
– Data Retention: 20 years at 85°C/ 100 years at 25°C
– Programming Lock for Software Security
• Peripheral Features
– QTouch® Library Support for Capacitive Touch Sensing (8 Channels)
– Two 8-bit Timer/Counters with two PWM Channels, Each
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– 10-bit ADC
• 4 Single-ended Channels
– Universal Serial Interface
– Boost Converter
• Special Microcontroller Features
– debugWIRE On-chip Debug System
– In-System Programmable via SPI Port
– External and Internal Interrupt Sources
– Pin Change Interrupt on 16 Pins
– Low Power Idle, ADC Noise Reduction and Power-down Modes
– Enhanced Power-on Reset Circuit
– Programmable Brown-out Detection Circuit
– Internal Calibrated Oscillator
– Temperature Sensor On-chip
• I/O and Packages
– Available in 20-pin SOIC and 20-pin QFN/MLF
– 16 Programmable I/O Lines
• Operating Voltage:
– 0.7 – 1.8V (via On-chip Boost Converter)
– 1.8 – 5.5V (Boost Converter Bypassed)
• Speed Grade
– Using On-chip Boost Converter
• 0 – 4 MHz
– External Power Supply
• 0 – 4 MHz @ 1.8 – 5.5V
• 0 – 8 MHz @ 2.7 – 5.5V
• Low Power Consumption
– Active Mode, 1 MHz System Clock
• 400 µA @ 3V (Without Boost Converter)
– Power-down Mode
• 150 nA @ 3V (Without Boost Converter)
8-bit
Microcontroller
with 4K Bytes
In-System
Programmable
Flash and Boost
Converter
ATtiny43U
Rev. 8048C–AVR–02/12
1 page  
ATtiny43U
architecture is more code efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers.
The ATtiny43U provides the following features: 4K byte of In-System Programmable Flash, 64
bytes EEPROM, 256 bytes SRAM, 16 general purpose I/O lines, 32 general purpose working
registers, two 8-bit Timer/Counters with two PWM channels, Internal and External Interrupts, a
4-channel 10-bit ADC, Universal Serial Interface, a programmable Watchdog Timer with internal
Oscillator, internal calibrated oscillator, and three software selectable power saving modes. The
Idle mode stops the CPU while allowing the SRAM, Timer/Counter, ADC, Analog Comparator,
and Interrupt system to continue functioning. The Power-down mode saves the register con-
tents, disabling all chip functions until the next Interrupt or Hardware Reset. The ADC Noise
Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise
during ADC conversions.
A special feature of ATtiny43U is the built-in boost voltage converter, which provides 3V supply
voltage from an external, low voltage.
The device is manufactured using Atmel’s high density non-volatile memory technology. The
On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI
serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code
running on the AVR core.
The ATtiny43U AVR is supported by a full suite of program and system development tools
including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators,
and Evaluation kits.
8048C–AVR–02/12
5
5 Page 
ATtiny43U
Figure 4-3. The X-, Y-, and Z-registers
X-register
15
7
R27 (0x1B)
XH
07
R26 (0x1A)
XL
0
0
Y-register
15
7
R29 (0x1D)
YH
07
R28 (0x1C)
YL
0
0
Z-register
15
7
R31 (0x1F)
ZH
0
7
R30 (0x1E)
ZL
0
0
In the different addressing modes these address registers have functions as fixed displacement,
automatic increment, and automatic decrement (see the instruction set reference for details).
4.6 Stack Pointer
The Stack is mainly used for storing temporary data, local variables and return addresses for
interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack,
in the data SRAM Stack area where the subroutine and interrupt stacks are located.
The Stack in the data SRAM must be defined by the program before any subroutine calls are
executed or interrupts are enabled. The Stack Pointer must be set to point above start of the
SRAM (see Figure 5-2 on page 16). The initial Stack Pointer value equals the last address of the
internal SRAM.
Note that the Stack is implemented as growing from higher to lower memory locations. This
means a Stack PUSH command decreases the Stack Pointer. See Table 4-1.
Table 4-1. Stack Pointer instructions
Instruction Stack pointer
PUSH
Decremented by 1
CALL
ICALL
RCALL
Decremented by 2
POP
Incremented by 1
RET
RETI
Incremented by 2
Description
Data is pushed onto the stack
Return address is pushed onto the stack with a
subroutine call or interrupt
Data is popped from the stack
Return address is popped from the stack with return
from subroutine or return from interrupt
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of
bits actually used is implementation dependent.
Note that the data space in some implementations of the AVR architecture is so small that only
SPL is needed. In this case, the SPH Register will not be present.
8048C–AVR–02/12
11
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