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PDF AT91SAM7L128 Data sheet ( Hoja de datos )
| Número de pieza | AT91SAM7L128 | |
| Descripción | (AT91SAM7L64 / AT91SAM7L128) AT91 ARM Thumb-based Microcontroller | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Incorporates the ARM7TDMI® ARM® Thumb® Processor
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Leader in MIPS/Watt
– EmbeddedICE™ In-circuit Emulation, Debug Communication Channel Support
• Internal High-speed Flash
– 128 Kbytes (AT91SAM7L128), Organized in 512 Pages of 256 Bytes Single Plane
– 64 Kbytes (AT91SAM7L64), Organized In 256 Pages of 256 Bytes Single Plane
– Single Cycle Access at Up to 15 MHz in Worst Case Conditions
– 128-bit Read Access
– Page Programming Time: 4.6 ms, Including Page Auto Erase, Full Erase Time: 10 ms
– 10,000 Write Cycles, 10-year Data Retention Capability, Sector Lock Capabilities,
Flash Security Bit
– Fast Flash Programming Interface for High Volume Production
• Internal High-speed SRAM, Single-cycle Access at Maximum Speed
– 6 Kbytes
• 2 Kbytes Directly on Main Supply That Can Be Used as Backup SRAM
• 4 Kbytes in the Core
• Memory Controller (MC)
– Enhanced Embedded Flash Controller, Abort Status and Misalignment Detection
• Enhanced Embedded Flash Controller (EEFC)
– Interface of the Flash Block with the 32-bit Internal Bus
– Increases Performance in ARM and Thumb Mode with 128-bit Wide Memory
Interface
• Reset Controller (RSTC)
– Based on Zero-power Power-on Reset and Fully Programmble Brownout Detector
– Provides External Reset Signal Shaping and Reset Source Status
• Clock Generator (CKGR)
– Low-power 32 kHz RC Oscillator, 32 kHz On-chip Oscillator, 2 MHz Fast RC
Oscillator and one PLL
• Supply Controller (SUPC)
– Minimizes Device Power Consumption
– Manages the Different Supplies On Chip
– Supports Multiple Wake-up Sources
• Power Management Controller (PMC)
– Software Power Optimization Capabilities, Including Active and Four Low Power
Modes:
• Idle Mode: No Processor Clock
• Wait Mode: No Processor Clock, Voltage Regulator Output at Minimum
• Backup Mode: Voltage Regulator and Processor Switched Off
• Off (Power Down) Mode: Entire Chip Shut Down Except for Force Wake Up Pin
(FWUP) that Re-activates the Device. 100 nA Current Consumption.
• In Active Mode, Dynamic Power Consumption <30 mA at 36 MHz
– Three Programmable External Clock Signals
– Handles Fast Start Up
AT91 ARM
Thumb-based
Microcontroller
AT91SAM7L128
AT91SAM7L64
Summary
Preliminary
NOTE: This is a summary document.
The complete document is available on
the Atmel website at www.atmel.com..
6257AS–ATARM–28-Feb-08
1 page  
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3. Signal Description
AT91SAM7L128/64 Preliminary
Table 3-1. Signal Description List
Signal Name Function
Type
Active
Level
Power
VDDIO1
I/O Lines (PIOC) and Voltage Regulator
Power Supply
Power
VDDOUT
Voltage Regulator Output
Power
VDDCORE
Core Power Supply
Power
VDDINLCD
Charge Pump Power Supply
Power
VDD3V6
Charge Pump Output
Power
VDDLCD
LCD Voltage Regulator Power Supply
Power
VDDIO2
LCD Voltage Regulator Output
and
LCD I/O Lines Power Supply (PIOA and
PIOB)
Power
CAPP1
Charge pump capacitor 1
Power
CAPM1
Charge pump capacitor 1
Power
CAPP2
Charge pump capacitor 2
Power
CAPM2
Charge pump capacitor 2
Power
FWUP
Force Wake-up
Input
Low
WKUP0-15
Wake-up inputs used in Backup mode and
Fast Start-up inputs in Wait mode
Input
GND
Ground
Ground
Clocks, Oscillators and PLLs
XIN 32 kHz Oscillator Input
Input
XOUT
32 kHz Oscillator Output
Output
CLKIN
Main Clock input
Input
PCK0 - PCK2 Programmable Clock Output
Output
PLLRC
PLL Filter
Input
PLLRCGND PLL RC Filter Ground
Power
TCK
TDI
TDO
TMS
JTAGSEL
ERASE
ICE and JTAG
Test Clock
Input
Test Data In
Input
Test Data Out
Output
Test Mode Select
Input
JTAG Selection
Input
Flash Memory
Flash and NVM Configuration Bits Erase
Command
Input
High
Voltage
Reference Comments
From 1.80V to 3.6V
Connected externally to VDDOUT
From 1.80V to 3.6V
1.80V to 3.6V
Capacitor needed between CAPP1
and CAPM1.
VDDIO1
Capacitor needed between CAPP2
and CAPM2.
Needs external Pull-up.
VDDIO1
VDDIO1
VDDIO1
VDDIO1
Should be tied low when not used.
VDDCORE
Must not be connected to external
Ground.
VDDIO1
VDDIO1
VDDIO1
VDDIO1
VDDIO1
No internal pull-up resistor
No internal pull-up resistor
No internal pull-up resistor
Internal Pull-down resistor
VDDIO1 Internal Pull-down (15 kΩ) resistor
6257AS–ATARM–28-Feb-08
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4.4 144-ball LFBGA Pinout
AT91SAM7L128/64 Preliminary
Table 4-2. SAM7L128/64 Pinout for 144-ball LFBGA Package
Pin Signal Name
Pin Signal Name
Pin
A1 XOUT
D1 PA6
G1
A2 XIN
D2 PA5
G2
A3 VDDCORE
D3 PA7
G3
A4 GND
D4 NC
G4
A5 PLLRCGND
D5 PC26/PGMD15
G5
A6 PLLRC
D6 PC25/PGMD14
G6
A7 PC24/PGMD13
D7 PC21/PGMD11
G7
A8 PC23//PGMD12
D8 PC18/PGMD7
G8
A9 PC17/PGMD6
D9 PC6/PGMNVALID
G9
A10 NC
D10 PC7/PGMM0
G10
A11 PC14
D11 PC4/PGMRDY
G11
A12 PC12
D12 PC3/PGMNCMD
G12
B1 PA1
E1 VDDIO2
H1
B2 PA0
E2 PA10
H2
B3 NRSTB
E3 PA9
H3
B4 TEST
E4 PA11
H4
B5 TDO
E5 PA8
H5
B6 PC27
E6 VDDIO1
H6
B7 GND
E7 VDDIO1
H7
B8 NC
E8 VDDIO1
H8
B9 PC20/PGMD9
E9 PC5/PGMNOE
H9
B10 PC15/PGMD4
E10 PC0/PGMEN0
H10
B11 PC13/PGMD2
E11 PC2/PGMEN2
H11
B12 PC11/PGMD0
E12 VDDCORE
H12
C1 PA3
F1 VDDLCD
J1
C2 PA4
F2 PA13
J2
C3 PA2
F3 PA14
J3
C4 CLKIN
F4 PA12
J4
C5 FWUP
F5 GND
J5
C6 TDI
F6 GND
J6
C7 PC22/PGMD11
F7 GND
J7
C8 PC19/PGMD8
F8 VDDIO1
J8
C9 PC16/PGMD5
F9 TCK
J9
C10 PC9/PGMM2
F10 JTAGSEL
J10
C11 PC10/PGMM3
F11 PC1/PGMEN1
J11
C12 PC8/PGMM1
F12 VDDIO1
J12
Signal Name
VDD3V6
PA17
PA16
PA15
GND
GND
GND
VDDIO1
NRST
TMS
ERASE
VDDOUT
CAPM2
PA22
PA19
PA18
GND
GND
GND
VDDCORE
PC29
VDDCORE
PC28
AD0
CAPP2
PA23
PA24
PA21
PA20
PB8
PB9
PB14
VDDCORE
VDDCORE
VDDCORE
AD1
Pin Signal Name
K1 CAPM1
K2 VDDIO2
K3 VDDIO2
K4 PA25
K5 PB3
K6 PB10
K7 PB13
K8 PB15
K9 PB20
K10 VDDCORE
K11 VDDCORE
K12 AD2
L1 CAPP1
L2 VDDIO2
L3 VDDIO2
L4 PB4
L5 PB5
L6 PB11
L7 PB12
L8 PB17
L9 PB19
L10 PB22
L11 PB23
L12 AD3
M1 VDDINLCD
M2 PB0
M3 PB1
M4 PB2
M5 PB6
M6 PB7
M7 VDDIO2
M8 PB16
M9 PB18
M10 PB21
M11 GND
M12 ADVREF
6257AS–ATARM–28-Feb-08
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AT91SAM7L128.PDF ] | |
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