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PDF AT91SAM9XE512 Data sheet ( Hoja de datos )
| Número de pieza | AT91SAM9XE512 | |
| Descripción | (AT91SAM9XExxx) AT91 ARM Thumb Microcontrollers | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Incorporates the ARM926EJ-S™ ARM® Thumb® Processor
– DSP instruction Extensions, ARM Jazelle® Technology for Java® Acceleration
– 8 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer
– 200 MIPS at 180 MHz
– Memory Management Unit
– EmbeddedICE™, Debug Communication Channel Support
• Additional Embedded Memories
– One 32 Kbyte Internal ROM, Single-cycle Access at Maximum Matrix Speed
– One 32 Kbyte (for AT91SAM9XE256 and AT91SAM9XE512) or 16 Kbyte (for
AT91SAM9XE128) Internal SRAM, Single-cycle Access at Maximum Matrix Speed
– 128, 256 or 512 Kbytes of Internal High-speed Flash for AT91SAM9XE128,
AT91SAM9XE256 or AT91SAM9XE512 Respectively. Organized in 256, 512 or 1024
Pages of 512 Bytes Respectively.
• 128-bit Wide Access
• Fast Read Time: 60 ns
• Page Programming Time: 4 ms, Including Page Auto-erase,
Full Erase Time: 10 ms
• 10,000 Write Cycles, 10 Years Data Retention, Page Lock Capabilities, Flash
Security Bit
• Enhanced Embedded Flash Controller (EEFC)
– Interface of the Flash Block with the 32-bit Internal Bus
– Increases Performance in ARM and Thumb Mode with 128-bit Wide Memory
Interface
• External Bus Interface (EBI)
– Supports SDRAM, Static Memory, ECC-enabled NAND Flash and CompactFlash™
• USB 2.0 Full Speed (12 Mbits per second) Device Port
– On-chip Transceiver, 2,688-byte Configurable Integrated DPRAM
• USB 2.0 Full Speed (12 Mbits per second) Host Single Port in the 208-pin PQFP Device
and Double Port in 217-ball LFBGA Device
– Single or Dual On-chip Transceivers
– Integrated FIFOs and Dedicated DMA Channels
• Ethernet MAC 10/100 Base-T
– Media Independent Interface or Reduced Media Independent Interface
– 28-byte FIFOs and Dedicated DMA Channels for Receive and Transmit
• Image Sensor Interface
– ITU-R BT. 601/656 External Interface, Programmable Frame Capture Rate
– 12-bit Data Interface for Support of High Sensibility Sensors
– SAV and EAV Synchronization, Preview Path with Scaler, YCbCr Format
• Bus Matrix
– Six 32-bit-layer Matrix
– Remap Command
• Fully-featured System Controller, including
– Reset Controller, Shutdown Controller
– Four 32-bit Battery Backup Registers for a Total of 16 Bytes
– Clock Generator and Power Management Controller
– Advanced Interrupt Controller and Debug Unit
– Periodic Interval Timer, Watchdog Timer and Real-time Timer
AT91 ARM
Thumb
Microcontrollers
AT91SAM9XE128
AT91SAM9XE256
AT91SAM9XE512
Preliminary
Summary
NOTE: This is a summary document.
The complete document is available on
the Atmel website at www.atmel.com.
6254AS–ATARM–14-Feb-08
1 page  
AT91SAM9XE128/256/512 Preliminary
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Figure 2-1. AT91SAM9XE128/256/512 Block Diagram
6254AS–ATARM–14-Feb-08
5
5 Page 
AT91SAM9XE128/256/512 Preliminary
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4. Package and Pinout
The AT91SAM9XE128/256/512 is available in a 208-pin PQFP Green package (0.5mm pitch) or
in a 217-ball LFBGA Green package (0.8 mm ball pitch).
4.1 208-pin PQFP Package Outline
Figure 4-1 shows the orientation of the 208-pin PQFP package.
A detailed mechanical description is given in the section “AT91SAM9XE Mechanical Character-
istics” of the product datasheet.
Figure 4-1.
208-pin PQFP Package Outline (Top View)
156 105
157 104
208
1
53
52
6254AS–ATARM–14-Feb-08
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