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PDF IP100ALF Data sheet ( Hoja de datos )
| Número de pieza | IP100ALF | |
| Descripción | Integrated 10/100 Ethernet MAC PHY | |
| Fabricantes | IC Plus | |
| Logotipo |  |
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IP100A LF
Preliminary Data Sheet
Integrated 10/100 Ethernet MAC + PHY
Features
Single chip 10/100BASE, half or full duplex
Ethernet Media Access Controller
IEEE
802.3
compliant
100BASE-TX/100BASE-FX/10BASE-T
PCI Bus master scatter/gather DMA on any
byte boundary
Full operation with PCI Clock from 25 MHz to
33 MHz
PCI Revision 2.2 compliant
On-chip transmit and receive FIFO buffers
On-chip LED drivers
Power management capabilities for ACPI 1.0
compliant systems
WakeOnLAN support
Management statistics gathering
IP multicast receive and filter support using
64 bit hash table
Transmit polling
Auto pad insertion for short packets
Programmable minimum Inter Packet Gap
Supports auto MDI-MDIX function
Smart Cable Analyzer (SCA) Support
Capable of using 93C46 EEPROM
On-chip crystal oscillator
On-chip voltage regulator
2.5/3.3V CMOS with 5V tolerant I/O
0.25µm technology
128-pin PQFP
Support Lead Free package (Please refer to
the Order Information)
General Description
The IP100A LF is a single-chip, full duplex,
10/100Mbps Ethernet MAC + PHY incorporating a
32-bit PCI with bus master support. The IP100A
LF is designed for use in a variety of applications
including workstation NICs, PC motherboards,
and other systems utilizing a PCI bus that require
network connectivity to an Ethernet or Fast
Ethernet LAN.
The IP100A LF includes a PCI bus interface unit,
IEEE 802.3 compliant MAC, transmit and receive
FIFO buffers, IEEE 802.3 compliant 100BASE-TX,
10BASE-T, and 100BASE-FX PHY, serial
EEPROM interface and LED drivers.
The IP100A LF implements a rich set of control
and status registers. Accessible via the PCI
interface, these registers provide a host system
visibility into the features and operating state of
the IP100A LF. Network management statistics
are also recorded, and host access to registers of
the PHY device are facilitated through the IP100A
LF’s PCI interface.
The IP100A LF supports features for use in
“Green PCs” or systems where control over
system power consumption is desired. The
IP100A LF supports several power down states,
and the ability to issue a system “wake event” via
reception of unique, user defined Ethernet frames.
In addition, the IP100A LF can assert a wake
event in response to changes in the Ethernet link
status
Copyright © 2004, IC Plus Corp.
1/97
March. 30, 2007
IP100A LF-DS-R17
1 page  
www.DataSheet4U.com
IP100A LF
Preliminary Data Sheet
11.6
LAN PCI Configuration Registers ........................................................................... 75
11.6.1
CacheLineSize........................................................................................................ 76
11.6.2
CapId ...................................................................................................................... 76
11.6.3
CapPtr..................................................................................................................... 76
11.6.4
CISPointer............................................................................................................... 77
11.6.5
ClassCode .............................................................................................................. 77
11.6.6
ConfigCommand..................................................................................................... 78
11.6.7
ConfigStatus ........................................................................................................... 79
11.6.8
Data ........................................................................................................................ 80
11.6.9
DeviceId .................................................................................................................. 80
11.6.10 ExpRomBaseAddress............................................................................................. 81
11.6.11 HeaderType ............................................................................................................ 81
11.6.12 InterruptLine............................................................................................................ 82
11.6.13 InterruptPin ............................................................................................................. 82
11.6.14 IoBaseAddress ....................................................................................................... 82
11.6.15 LatencyTimer .......................................................................................................... 83
11.6.16 MaxLat .................................................................................................................... 83
11.6.17 MemBaseAddress .................................................................................................. 83
11.6.18 MinGnt .................................................................................................................... 84
11.6.19 NextItemPtr ............................................................................................................. 84
11.6.20 PowerMgmtCap ...................................................................................................... 85
11.6.21 PowerMgmtCtrl ....................................................................................................... 86
11.6.22 RevisionId ............................................................................................................... 86
11.6.23 SubsystemId ........................................................................................................... 87
11.6.24 SubsystemVendorId ............................................................................................... 87
11.6.25 VendorId ................................................................................................................. 87
11.7
EEPROM Data Format ........................................................................................... 88
11.7.1
AsicCtrl.................................................................................................................... 88
11.7.2
ConfigParm ............................................................................................................. 89
11.7.3
FunctionsCtrl........................................................................................................... 90
11.7.4
StationAddress ....................................................................................................... 90
11.7.5
SubsystemId ........................................................................................................... 91
11.7.6
SubsystemVendorId ............................................................................................... 91
12 Signal Requirements........................................................................................................................... 92
12.1
Absolute Maximum Ratings .................................................................................... 92
12.2
Operating Ranges................................................................................................... 92
12.3
AC Characteristics .................................................................................................. 94
12.4
Thermal Data .......................................................................................................... 96
13 Order Information ................................................................................................................................ 96
14 Physical Dimensions ........................................................................................................................... 97
Copyright © 2004, IC Plus Corp.
5/97
March. 30, 2007
IP100A LF-DS-R17
5 Page 
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IP100A LF
Preliminary Data Sheet
PIN Descriptions (continued)
PIN NAME PIN TYPE
PIN DESCRIPTION
LED DRIVERS (continued)
LED_10N
OUTPUT
10Mb/sec Connection Status LED. This pin will output LOW to indicate
10Mb/sec Transmission if the connection between 2 devices have
negoatiated to link at 10Mb/sec.
LED_100N
LED_LINK
OUTPUT
OUTPUT
100Mb/sec Connection Status LED. This pin will output LOW to indicate
100Mb/sec Transmission if the connection between 2 devices have
negoatiated to link at 100Mb/sec.
Link Status LED. LED_LINK is the link status LED driver. The functionality
of the link status LED signal is based on the LEDMode bit of the AsicCtrl
register. A 4.7K pull-down resistor is placed between this pin and GND
regardless of whether the LED is connected to this pin.
MDI
RXP
RXN
TXP
INPUT
INPUT
OUTPUT
Receive input. When in 100BASE-TX mode, this receives MLT3 data from
the isolation transformer. When in 100BASE-FX mode, this is a PECL input.
Receive input. When in 100BASE-TX mode, this receives MLT3 data from
the isolation transformer. When in 100BASE-FX mode, this is a PECL input.
Transmit output. When in 100BASE-TX mode, this is an MLT-3 driver.
When in 100BASE-FX mode, this is a PECL driver.
TXN
OUTPUT Transmit output. When in 100BASE-TX mode, this is an MLT-3 driver.
When in 100BASE-FX mode, this is a PECL driver.
FFSD
INPUT
This pin is used to select TP or Fiber mode. For 100BASE-FX applications,
FFSD is connected to the signal detect output pin of a fiber optic module at
PECL level. Connecting this pin to GND will force the IP100A into TP
mode.
MISCELLANEOUS
CTRL25
OUTPUT
LAST_GASPN INPUT
X1
X2
ISET
OSCIN
OSCOUT
ANALOG
This is a controller pin to monitor correct 2.5V supply to IC.
This pin monitors the PCI voltage. If the voltage is dropped to certain value,
LAST_GASPN will indicate IP100A LF to transmit LAST GASP frame to inform
the other end that IP100A LF is not functioning till SYSTEM POWER ON or
RESET.
25MHz Crystal Oscillator Input. The external 25MHz crystal and capacitor
is connected to the on-chip crystal oscillator circuit through X1 input.
Alternately, X1 can be driven by an external clock source.
25MHz Crystal Oscillator Output. The external crystal and capacitor is also
connected to the output of the on-chip crystal oscillator circuit through X2.
When X1 is driven by an external clock source, X2 should be left unconnected.
Band Gap Resistor. Connect a 6.2kohm, 1% resister between ISET and GND.
TEST
INPUT
Test. Enables the IP100A LF test modes.
NC Reserved. These Pins must keep floating at application circuit.
POWER AND GROUND
VCC2
POWER +3.3 volt I/O power supply.
VCC1
POWER +2.5 volt digital logic power supply.
AVCC25
POWER +2.5 volt analog power supply.
AVCC33
AVSS
POWER +3.3 volt analog power supply.
GROUND Analog Ground
Copyright © 2004, IC Plus Corp.
11/97
March. 30, 2007
IP100A LF-DS-R17
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