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PDF IP101ALF Data sheet ( Hoja de datos )
| Número de pieza | IP101ALF | |
| Descripción | Single port 10/100 Fast Ethernet Transceiver | |
| Fabricantes | IC Plus | |
| Logotipo |  |
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IP101A LF
Data Sheet
Single port 10/100 Fast Ethernet Transceiver
Features
10/100Mbps TX
Full-duplex or half-duplex
Supports Auto MDI/MDIX function
Fully compliant with IEEE 802.3/802.3u
Supports IEEE 802.3u auto-negotiation
Supports MII / RMII / SNI interface
IEEE 802.3 full duplex control specification
Supports Automatic Power Saving mode
Supports BaseLine Wander (BLW)
compensation
Supports Interrupt function
Supports repeater mode
Single 3.3V power supply with built-in 2.5V
regulator
DSP-based PHY Transceiver technology
Using either 25MHz crystal/oscillator or
50MHz oscillator REF_CLK as clock source
Flexible LED display for speed, duplex, link,
activity and collision
Supports flow control to communicate with
other MAC through MDC and MDIO
0.25u, CMOS technology
48-pin LQFP
Support Lead Free package (Please refer to
the Order Information)
General Description
IP101A LF is an IEEE 802.3/802.3u compliant
single-port Fast Ethernet Transceiver for both
100Mbps and 10Mbps operations. It supports
Auto MDI/MDIX function to simplify the network
installation and reduce the system maintenance
cost. To improve the system performance, IP101A
LF provides a hardware interrupt pin to indicate
the link, speed and duplex status change. IP101A
LF also provides Media Independent Interface
(MII) / Serial Network Interface (SNI) or Reduced
Media Independent Interface (RMII) to connect
with different types of 10/100Mbps Media Access
Controller (MAC). IP101A LF is designed to use
category 5 unshielded twisted-pair cable
connecting to other LAN devices.
IP101A LF Transceiver is fabricated with
advanced CMOS technology, which the chip only
requires 3.3V as power supply and consumes
very low power in the Auto Power Saving mode.
IP101A LF can be implemented as Network
Interface Adapter with RJ-45 for twisted-pair
connection. It can also be easily implemented into
HUB, Switch, Router, Access Point.
Copyright © 2004, IC Plus Corp.
1/36
Oct 22, 2007
IP101A LF-DS-R12
1 page  
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Pin Assignments
IP101A LF
Data Sheet
37. AN_ENA
38. DPLX
39. SPD
40. RPTR
41. APS
42. RESET_N
43. ISOL
44. MII_SNIB
45. DGND
46. X1
47. X2
48. INTR
IP101A LF
Fast Ethernet Single Phy Transceiver Chip
48 pins LQFP package
24. RX_ER
23. CRS
/LEDMOD
22. RX_DV
/CRS_DV
21. RXD0
20. RXD1
19. RXD2
18. RXD3
17. DGND
16. RX_CLK/
C50M_O
15. LED4/
PHYAD4
14. DVDD33
13. LED3/
PHYAD3
Figure 2 : IP101A LF pins assignment
Copyright © 2004, IC Plus Corp.
5/36
Oct 22, 2007
IP101A LF-DS-R12
5 Page 
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IP101A LF
Data Sheet
Pin Descriptions (continued)
Pin no. Label
Type Description
Clock and Miscellaneous - Crystal Input/Output Pins
47 X2
O 25MHz Crystal Output: Connects to crystal to provide the
25MHz output. It must be left open when X1 is driven with an
external 25MHz oscillator.
46 X1
I 25MHz Crystal Input: Connects to crystal to provide the 25MHz
crystal input. If a 25MHz oscillator is used, connect X1 to the
oscillator’s output. If a 50MHz clock is applied to pin7, X1 should
be connected to VSS or 2.5v VDD. Please refer to the clock
source description.
Clock and Miscellaneous - Miscellaneous Pins
42 RESET_N
I RESET_N: Enable a low status signal will reset the chip. For a
complete reset function. 25MHz clock (x1) must be active for a
minimum of 10 clock cycles before the rising edge of RESET_N.
Chip will be able to operate after 2.5ms delay of the rising edge
of RESET_N. The 2.5ms extention is to ensure the stability of
system power.
48 INTR
O Interrupt Pin: When the MII register 17:<15> is set to high, this
(OD) pin is used as an interrupt pin (Notice: this is an open drain
output, so an external pulled-up resistor is needed)
27 TEST_ON
(PD)
Test Enable: Set this pin to high to enable test mode, while for
normal operation, this pin does not need to be connected. (An
internal weak pulled-down is used to disable test mode as a
default)
28 ISET
I Transmit Bias Resistor Connection: This pin should be
connected to GND via a 6.2KΩ (1%) resistor to define driving
current for transmit DAC.
Copyright © 2004, IC Plus Corp.
11/36
Oct 22, 2007
IP101A LF-DS-R12
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