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PDF SX1223 Data sheet ( Hoja de datos )
| Número de pieza | SX1223 | |
| Descripción | 425 - 475 MHz / 850 - 950 MHz Integrated UHF Transmitter | |
| Fabricantes | Semtech Corporation | |
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SX1223
SX1223
425 – 475 MHz / 850 – 950 MHz
Integrated UHF Transmitter
GENERAL DESCRIPTION
The SX1223 is a single chip transmitter operating in
UHF frequency bands including the 434, 869 and 915
MHz license-free ISM (Industrial Scientific and
Medical) bands. Its highly integrated architecture
allows for minimum external components while
maintaining design flexibility. All major RF
communication parameters are programmable and
most of them can be set dynamically. The SX1223
offers the advantage of high data rate communication
at rates of up to 153.6 kbit/s. The SX1223 is
optimized for low cost applications while offering high
RF output power. The device is suitable for
applications which have to satisfy either the European
(ETSI-300-220) or the North American (FCC part 15)
regulatory standards.
APPLICATIONS
• Automated Meter Reading (AMR)
• Home Automation and Access Control
• High-Quality Speech, Music and Data over RF
KEY PRODUCT FEATURES
• RF output power: up to +10 dBm
• Low power consumption:
TX = 25.8 mA @ 10 dBm (typical)
• Supply voltage down to 2.0 V
• Data rate from 1.2 to 153.6 kbit/s
• On-chip frequency synthesizer
• Continuous phase 2-level FSK modulation
• Very small RoHS green package (TQFN24, 4mm
x 4mm)
ORDERING INFORMATION
Part number
Temperature
range
Package
SX1223I073TRT(1) -40 °C to +85 °C TQFN24
(1) TR refers to tape & reel.
T refers to Lead Free package.
This device is WEEE and RoHS compliant.
Rev 5 May 2007
www.semtech.com
1 page  
SX1223
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3 ELECTRICAL CHARACTERISTICS
3.1 ABSOLUTE MAXIMUM OPERATING RANGES
Stresses above the values listed below may cause permanent device failure. Exposure to absolute maximum
ratings for extended periods may affect device reliability.
Symbol
VDDmax
Tmax
Description
Supply voltage
Storage temperature
Min.
-0.4
-55
Max.
3.9
125
Unit
V
°C
The device is ESD sensitive and should be handled with precaution.
3.2 SPECIFICATIONS
3.2.1 Operating Range
Symbol
VDD
T
CLop
Description
Supply voltage (*)
Temperature
Load capacitance on digital ports
(*) Divided in two ranges:
- (sv1) high range, 2.2 V – 3.6 V, using on-chip regulators,
- (sv2) low range, 2.0 V – 2.5 V, without using the regulators.
Min.
2.0
-40
-
Max.
3.6
85
25
Unit
V
°C
pF
3.2.2 Electrical Specifications
The table below gives the electrical specifications of the transmitter under the following conditions:
Supply Voltage = 3.3 V, temperature = 25 °C, 2-leve l FSK, fc = 915 MHz, Output power = 10 dBm, Bit rate = 38.4
kb/s, ∆f = 100 kHz, XTAL = 16 MHz, modulation by pulling the VCO in open loop (mw2), and conditions as defined
in section 6, unless otherwise specified.
Symbol
IDDSL
IDDST
IDDFS
IDDT
FR
FDA
FDA_L
∆FDA
BR
BR_3
SPICLK
Description
Conditions
Min Typ Max
Supply current in sleep
mode
- 0.3 1
Supply current in standby
mode
Crystal oscillator running,
CLKOUT off
- 0.2 0.3
Supply current in FS mode Frequency synthesizer
running
-5 6
Supply current during
transmission
10 dBm
0dBm
-
-
25.8
14
-
-
Frequency range
425 -
475
850 -
950
Frequency deviation
For FR from 850 to 950 MHz 5
- 255
Frequency deviation
For FR from 425 to 475 MHz 5
- 200
Variation of frequency
deviation
- 15 - + 15
Bit rate
Modulation modes mw1 mw2 1.2
- 153.6
Bit rate for mw3 mode
Modulation mode mw3
1.2 - 19.2
SPI clock frequency (SCK) SCK duty cycle 50% +/-10%
1
Unit
µA
mA
mA
mA
mA
MHz
MHz
kHz
kHz
%
kbit/s
kbit/s
MHz
© Semtech 2007
www.semtech.com
5
5 Page 
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CPOUT, pin 20
R2
VARIN, pin 21
C1 C2
R1
C3
CPOUT, pin 20
C1 C2
R1
VARIN, pin 21
47nF C3
SX1223
a) b)
Figure 5: Loop filter for a) closed loop modulation and b) open loop modulation
4.1.6 Lock Detect
A lock detector can be enabled by setting LD_en=1. When enabled pin LD is set high, indicating that the PLL is in
lock. The lock detect signal can also be used to control the PA; if LD is low the PA is turned off and vice versa. To
enable this function, the PA_LDc_en must be set to ‘1’ (see section 4.3).
Care must be taken when monitoring the LD during data transmission using the closed loop modulation. The LD
may show that the PLL is not locked, especially when the loop filter bandwidth is too high relative to the bit rate.
4.2 MODULATOR
4.2.1 Introduction
The modulator has a high degree of flexibility, and there are thus several values that need programming. First, the
settings concerning the data bit rate must be determined, then these values will be used in the calculation of the
frequency deviation. Finally the user must check that the modulator won’t saturate with the values chosen.
4.2.2 Data Interface
The "data interface" can be programmed to synchronous or asynchronous mode (see Table 4).
Sync_en
0
1
State
DataClk pin off
DataClk pin on.
Comments
Transparent transmission of data
Bit-clock is generated by transmitter
Table 4: Synchronizer mode
In asynchronous mode only the DATAIN pin is used for transmitting the data to the SX1223.
In synchronous mode the SX1223 is defined as "Master" and provides a data clock on pin DCLK that allows the
user to utilize low cost micro controller reference frequency. The data interface is defined in such a way that all user
actions should take place on falling edges of DCLK as illustrated in Figure 6. The data are sampled by the SX1223
on the rising edges of DCLK.
DATAIN
DCLK
Figure 6: Time diagram of the data interface in synchronous mode
Before entering into transmit mode (mw1 or mw2), it is important to set DATAIN to high impedance. The data is
provided directly to the modulation circuit and violation of this may cause abnormal behavior.
© Semtech 2007
www.semtech.com
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| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet SX1223.PDF ] | |
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