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PDF ADE7518 Data sheet ( Hoja de datos )
| Número de pieza | ADE7518 | |
| Descripción | Single-Phase Energy Measurement IC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ADE7518 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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Single-Phase Energy Measurement IC with
8052 MCU, RTC, and LCD Driver
ADE7518
GENERAL FEATURES
Wide supply voltage operation: 2.4 V to 3.7 V
Internal bipolar switch between regulated and battery inputs
Ultralow power operation with power saving modes
Full operation: 4 mA to 1.6 mA (PLL clock dependent)
Battery mode: 3.2 mA to 400 μA (PLL clock dependent)
Sleep mode
Real-time clock (RTC) mode: 1.5 μA
RTC and LCD mode: 27 μA
Reference: 1.2 V ± 0.1% (10 ppm/°C drift)
64-lead RoHS package option
Low profile quad flat package (LQFP)
Operating temperature range: −40°C to +85°C
ENERGY MEASUREMENT FEATURES
Proprietary analog-to-digital converters (ADCs) and digital
signal processing (DSP) provide high accuracy active
(WATT), reactive (VAR), and apparent energy (VA)
measurement
Less than 0.1% error on active energy over a dynamic
range of 1000 to 1 @ 25°C
Less than 0.5% error on reactive energy over a dynamic
range of 1000 to 1 @ 25°C
Less than 0.5% error on root mean square (rms)
measurements over a dynamic range of 500 to 1 for
current (Irms) and 100 to 1 for voltage (Vrms) @ 25°C
Supports IEC 62053-21, IEC 62053-22, IEC 62053-23,
EN 50470-3 Class A, Class B, and Class C, and ANSI C12-16
Differential input with programmable gain amplifiers (PGAs)
supports shunts and current transformers
High frequency outputs proportional to Irms, active, reactive,
or apparent power (AP)
MICROPROCESSOR FEATURES
8052-based core
Single-cycle 4 MIPS 8052 core
8052-compatible instruction set
32.768 kHz external crystal with on-chip PLL
Two external interrupt sources
External reset pin
Low power battery mode
Wake-up from I/O, alarm, and universal asynchronous
receiver/transmitter (UART)
LCD driver operation
Real-time clock
Counter for seconds, minutes, and hours
Automatic battery switchover for RTC backup
Operation down to 2.4 V
Ultralow battery supply current: 1.5 μA
Selectable output frequency: 1 Hz to 16.384 kHz
Embedded digital crystal frequency compensation for
calibration and temperature variation: 2 ppm resolution
Integrated LCD driver
108-segment driver
2×, 3×, or 4× multiplexing
LCD voltages generated with external resistors
On-chip peripherals
UART, SPI or I2C, and watchdog timer
Power supply management with user-selectable levels
Memory: 16 kB flash memory, 512 bytes RAM
Development tools
Single-pin emulation
IDE-based assembly and C-source debugging
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.
1 page  
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ADE7518
SPECIFICATIONS
VDD = 3.3 V ± 5%, AGND = DGND = 0 V, on-chip reference XTAL = 32.768 kHz, TMIN to TMAX = −40°C to +85°C, unless otherwise noted.
ENERGY METERING
Table 1.
Parameter
Min Typ
Max Unit
MEASUREMENT ACCURACY1
Phase Error Between Channels
PF = 0.8 Capacitive
±0.05
Degrees
PF = 0.5 Inductive
±0.05
Degrees
Active Energy Measurement Error2
0.1 % of reading
AC Power Supply Rejection2
Output Frequency Variation
0.01 %
DC Power Supply Rejection2
Output Frequency Variation
0.01 %
Active Energy Measurement Bandwidth1
8
kHz
Reactive Energy Measurement Error2 0.5 % of reading
Vrms Measurement Error2
Vrms Measurement Bandwidth1
Irms Measurement Error2
Irms Measurement Bandwidth1
0.5 % of reading
3.9 kHz
0.5 % of reading
3.9 kHz
ANALOG INPUTS
Maximum Signal Levels
±400 mV peak
±400 mV peak
Input Impedance (DC)
770 kΩ
ADC Offset Error2
±10 mV
±1 mV
Gain Error2
Current Channel
−3 + 3 %
Voltage Channel
−3 + 3 %
Gain Error Match
±0.2 %
CF1 AND CF2 PULSE OUTPUT
Maximum Output Frequency
13.5 kHz
Duty Cycle
Active High Pulse Width
50 %
90 ms
Test Conditions/Comments
37° phase lead
60° phase lag
Over a dynamic range of 1000 to 1 @ 25°C
VDD = 3.3 V + 100 mV rms/120 Hz
IP = VP = ±100 mV rms
VDD = 3.3 V ± 117 mV dc
Over a dynamic range of 1000 to 1 @ 25°C
Over a dynamic range of 100 to 1 @ 25°C
Over a dynamic range of 500 to 1 @ 25°C
VP − VN differential input
IP − IN differential input
PGA1 = PGA2 = 1
PGA1 = 16
IP = 0.4 V dc or IP = 0.4 dc
Voltage channel = 0.4 V dc
VP − VN = 400 mV peak, IP − IN = 250 mV,
PGA1 = 2 sine wave
If CF1 or CF2 frequency, >5.55 Hz
If CF1 or CF2 frequency, <5.55 Hz
1 These specifications are not production tested but are guaranteed by design and/or characterization data on production release.
2 See the Terminology section for definition.
Rev. 0 | Page 5 of 128
5 Page 
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Table 7. SPI Master Mode Timing (SPICPHA = 0) Parameters
Parameter
Description
tSL SCLK low pulse width
tSH SCLK high pulse width
tDAV Data output valid after SCLK edge
tDOSU Data output setup before SCLK edge
tDSU Data input setup time before SCLK edge
tDHD Data input hold time after SCLK edge
tDF Data output fall time
tDR Data output rise time
tSR SCLK rise time
tSF SCLK fall time
Min
2SPIR × tCORE1
2SPIR × tCORE1
0
tCORE1
1 tCORE depends on the clock divider or CD[2:0] bits of the POWCON SFR (see Table 24); tCORE = 2CD/4.096 MHz.
ADE7518
Typ
(SPIR + 1) × tCORE1
(SPIR + 1) × tCORE1
19
19
19
19
Max
3 × tCORE1
75
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK
(SPICPOL = 0)
SCLK
(SPICPOL = 1)
MOSI
MISO
tSH tSL
tDOSU
MSB
tDAV
tDF
tDR
BITS [6:1]
tSR tSF
LSB
MSB IN
BITS [6:1]
LSB IN
tDSU tDHD
Figure 5. SPI Master Mode Timing (SPICPHA = 0)
Rev. 0 | Page 11 of 128
11 Page | ||
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