PDF TJA1082 Data sheet ( Hoja de datos )

Número de pieza	TJA1082
Descripción	FlexRay Node Transceiver
Fabricantes	NXP Semiconductors
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No Preview Available ! www.DataSheet4U.com TJA1082 FlexRay node transceiver Rev. 01 — 1 July 2009 Preliminary data sheet 1. General description The TJA1082 FlexRay node transceiver is compatible with the FlexRay electrical physical layer speciﬁcation V2.1 Rev. B (see Ref. 1). It also incorporates features and parameters anticipated to be included in V3.0, currently being ﬁnalized. It is primarily intended for communication systems operating at between 2.5 Mbit/s and 10 Mbit/s, and provides an advanced interface between the protocol controller and the physical bus in a FlexRay network. The TJA1082 offers an optimized solution for Electronic Control Unit (ECU) applications that do not need enhanced power management and are typically switched by ignition or activated by a dedicated wake-up line. The TJA1082 provides differential transmit capability to the network and differential receive capability to the FlexRay controller. It offers excellent EMC performance as well as high ESD protection. The TJA1082 actively monitors system performance using dedicated error and status information (readable by any microcontroller), as well as internal voltage and temperature monitoring. 2. Features 2.1 Optimized for time triggered communication systems I Compliant with Electrical Physical Layer speciﬁcation 2.1 Rev. B I Automotive product qualiﬁcation in accordance with AEC-Q100 (Grade 1) I Data transfer at 2.5 Mbit/s, 5 Mbit/s and 10 Mbit/s I Supports 60 ns minimum bit time at 400 mV differential voltage I Very low ElectroMagnetic Emission (EME) to support unshielded cable I Differential receiver with high common-mode range for excellent ElectroMagnetic Immunity (EMI) I Auto I/O level adaptation to host controller supply voltage VIO I Can be used in 14 V and 42 V powered systems I Instant shut down interface (BGE pin) 2.2 Low power management I Very low current consumption in Standby mode I Remote wake-up via wake-up symbol or dedicated FlexRay data frames on the bus lines 1 page www.DNatXaSPheSete4Um.coicmonductors TJA1082 FlexRay node transceiver Table 3. Pin signalling in the different power modes Mode Normal Standby STBN HIGH LOW LOW UV at VIO no no no UV at VCC no no yes[3] ERRN LOW HIGH error error ﬂag ﬂag set reset wake wake ﬂag ﬂag set reset wake wake ﬂag ﬂag set[4] reset[4] RXD LOW bus DATA_ 0 wake ﬂag set wake ﬂag set[4] HIGH bus DATA_1 or idle wake ﬂag reset wake ﬂag reset[4] SDO high- impedance (in simple error indication mode) or enabled (in SPI mode) Biasing BP, BM VCC / 2 GND HIGH no yes[3] error error ﬂag ﬂag set reset wake ﬂag set[4] wake ﬂag reset[4] X yes[5] no LOW X yes[5] yes[3] LOW LOW LOW high- impedance Power-off[6] X X[5] yes high- HIGH impedance GND[7] UV-det enabled Trans- mitter enabled Low- power receiver enabled[1] disabled enabled[2] disabled disabled enabled[2] disabled disabled [1] The wake ﬂag is set if a valid wake-up event is detected while switching to Standby mode. [2] The wake ﬂag is set if a valid wake-up event is detected. [3] Vuvd(VCC) > VCC > Vth(det)POR. [4] Pins ERRN and RXD will reﬂect the state of the wake ﬂag prior to the undervoltage event. [5] The internal signals at pins STBN, BGE and TXD are set LOW; the internal signals at pins TXEN, SCLK and SCSN are set HIGH. [6] VCC < Vth(rec)POR at power-up and VCC < Vth(det)POR at power-down (see Figure 6 and Figure 7). [7] Except when VCC = 0; in this case the biasing of BP and BM is ﬂoating. 6.1.1 Normal mode In Normal mode, the transceiver transmits and receives data via the bus lines BP and BM. The transmitter and the normal receiver are enabled, along with the undervoltage detection function. The timing diagram for Normal mode is illustrated in Figure 3. TJA1082_1 Preliminary data sheet Rev. 01 — 1 July 2009 © NXP B.V. 2009. All rights reserved. 5 of 35 5 Page www.DNatXaSPheSete4Um.coicmonductors TJA1082 FlexRay node transceiver 6.3 Remote wake-up 6.3.1 Bus wake-up via wake-up pattern A valid remote wake-up event occurs when a wake-up pattern is received. A wake-up pattern consists of at least two consecutive wake-up symbols. A wake-up symbol consists of a DATA_0 phase lasting longer than tdet(wake), followed by an idle phase lasting longer than tdet(wake)idle, provided both wake-up symbols occur within a time span of tdet(wake)tot (see Figure 8). The transceiver will also wake up if the idle phases are replaced by DATA_1 phases. Vdif (mV) +425 0 −425 < tdet(wake)tot > tdet(wake)idle wake-up > tdet(wake)idle > tdet(wake)DATA_0 > tdet(wake)DATA_0 +425 0 −425 > tdet(wake)idle > tdet(wake)idle > tdet(wake)DATA_0 > tdet(wake)DATA_0 Fig 8. Bus wake-up timing wake-up symbol wake-up symbol wake-up pattern 015aaa007 The wake-up mechanism of the TJA1082 follows the state transition diagram shown in Figure 9. See Ref. 1 for more details of the wake-up mechanism. TJA1082_1 Preliminary data sheet Rev. 01 — 1 July 2009 © NXP B.V. 2009. All rights reserved. 11 of 35 11 Page

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