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PDF KK4043B Data sheet ( Hoja de datos )
| Número de pieza | KK4043B | |
| Descripción | Quad 3-State R/S Latches High-Voltage Silicon-Gate CMOS | |
| Fabricantes | KODENSHI KOREA | |
| Logotipo |  |
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Quad 3-State R/S Latches
High-Voltage Silicon-Gate CMOS
TECHNICAL DATA
KK4043B
The KK4043B types are quad cross-coupled 3-state CMOS NOR
latces. Each latch has a separate Q output and individual SET and RESET
inputs. The Q outputs are controlled by a common ENABLE input. A
logic “1” or high on the ENABLE input connects the latch states to the Q
outputs. A logic “0” or low on the ENABLE input disconnects the latch
states from the Q outputs, resulting in an open circuit condition on the Q
outputs. The open circuit feature allows common busing of the outputs.
• Operating Voltage Range: 3.0 to 18 V
• Maximum input current of 1 µA at 18 V over full package-temperature
range; 100 nA at 18 V and 25°C
• Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
ORDERING INFORMATION
KK4043BN Plastic
KK4043BD SOIC
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 13 = NO CONNECTION
PIN 16=VCC
PIN 8= GND
FUNCTION TABLE
Inputs
S R OE
XX L
LL
LH
HL
HH
H
H
H
H
X = don’t care
Outputs
Q
High
Impedance
No change
L
H
H
1
1 page  
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KK4043B
TEST IN IN A
tPHZ VCC GND GND
tPLZ GND VCC VCC
tPZH VCC GND GND
tPZL GND VCC VCC
Figure 4. Test Circuit
EXPANDED LOGIC DIAGRAM
( 1/4 of the Device)
5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet KK4043B.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| KK4043B | Quad 3-State R/S Latches High-Voltage Silicon-Gate CMOS | KODENSHI KOREA |
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