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PDF ADM12914 Data sheet ( Hoja de datos )
| Número de pieza | ADM12914 | |
| Descripción | Quad UV/OV Positive/Negative Voltage Supervisor | |
| Fabricantes | Analog Devices | |
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Data Sheet
±0.8% Accurate Quad UV/OV
Positive/Negative Voltage Supervisor
ADM12914
FEATURES
Quad undervoltage/overvoltage (UV/OV) positive/negative
supervisor
Supervises up to two negative rails
Adjustable UV and OV input thresholds
Industry leading threshold accuracy over the extended
temperature range: ±0.8%
1 V buffered reference output
Open-drain UV and OV reset outputs
Adjustable reset timeout with disable option
Outputs guaranteed down to VCC of 0.9 V
Glitch immunity
62 µA supply current
16-lead QSOP package
Specified from −40°C to +125°C
APPLICATIONS
Server supply monitoring
FPGA/DSP core and I/O voltage monitoring
Telecommunications equipment
Medical equipment
FUNCTIONAL BLOCK DIAGRAM
VCC TIMER
ADM12914
VH1
500mV
TIMER
VL1
VH2
500mV
UV
VL2
VH3
OUTPUT
LOGIC
500mV
VL3
VH4
500mV
VL4
MUX
SEL GND
Figure 1.
OV
LOGIC
REF
LATCH/DIS
REF
GENERAL DESCRIPTION
The ADM12914 is a quad voltage supervisory IC ideally suited
for monitoring multiple rails in a wide range of applications.
Each monitored rail has two dedicated input pins, VHx and VLx,
which allows each rail to be monitored for both undervoltage
(UV) and overvoltage (OV) conditions with high threshold
accuracy of ±0.8%. Common active low undervoltage (UV) and
overvoltage (OV) pins are shared by each of the monitored
voltage rails.
The ADM12914 includes a 1 V buffered reference output, REF,
that acts as an offset when monitoring a negative voltage. The
three-state SEL pin determines the polarity of the third and
fourth inputs, that is, it configures the device to monitor
positive or negative supplies.
The device incorporates an internal shunt regulator that enables
the device to be used in higher voltage systems. This feature
requires a resistor to be placed between the main supply rail and
the VCC pin to limit the current flow into the VCC pin at a level
no greater than 10 mA. The ADM12914 uses the internal shunt
regulator to regulate VCC if the supply line exceeds the absolute
maximum ratings.
The ADM12914 is available in two models. The ADM12914-1
offers a latching overvoltage output that can be cleared by
toggling the LATCH input pin. The ADM12914-2 has a disable
pin that can override and disable both the UV and the OV
output signals.
The ADM12914 is available in a 16-lead QSOP package. The
device is specified over the extended temperature range of
−40°C to +125°C.
Rev. E
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2009–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADM12914
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Rating
VCC
UV, OV
−0.3 V to +6 V
−0.3 V to +16 V
TIMER
VLx, VHx, LATCH, DIS, SEL
−0.3 V to (VCC + 0.3 V)
−0.3 V to +7.5 V
ICC
Reference Load Current (IREF)
IUV, IOV
10 mA
±1 mA
10 mA
Storage Temperature Range
−65°C to +150°C
Operating Temperature Range
−40°C to +125°C
Lead Temperature (Soldering, 10 sec) 300°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
Data Sheet
Table 3. Thermal Resistance
Package Type
16-Lead QSOP
θJA
104
ESD CAUTION
Unit
°C/W
Rev. E | Page 4 of 16
5 Page 
ADM12914
MONITORING PIN CONNECTIONS
Positive Voltage Monitoring Scheme
When monitoring a positive supply, the desired nominal
operating voltage for monitoring is denoted by VM, IM is the
nominal current through the resistor divider, VOV is the over-
voltage trip point, and VUV is the undervoltage trip point.
VM
RX ADM12914
VNH
VHx
UVx
RY 0.5V
VNL
VLx
RZ
OVx
Figure 17. Positive Undervoltage/Overvoltage Monitoring Configuration
Figure 17 illustrates the positive voltage monitoring input con-
nection. Three external resistors, RX, RY, and RZ, divide the
positive voltage for monitoring,VM, into high-side voltage,
VPH, and low-side voltage, VPL. The high-side voltage is con-
nected to the corresponding VHx pin and the low-side voltage
is connected to the corresponding VLx pin.
To trigger an overvoltage condition, the low-side voltage (in this
case, VPL) must exceed the 0.5 V threshold on the VLx pin. The
low-side voltage, VPL, is given by the following equation:
VPL
= VOV R X
RZ
+ RY
+ RZ
= 0.5 V
Also,
RX
+ RY
+ RZ
=
VM
IM
Therefore, RZ, which sets the desired trip point for the overvoltage
monitor, is calculated using the following equation:
RZ
=
(0.5)(VM )
(VOV )(I M )
(1)
To trigger the undervoltage condition, the high-side voltage,
VPH, must exceed the 0.5 V threshold on the VHx pin. The
high-side voltage, VPH, is given by the following equation:
VPH
=
VUV
RY
RX +
+ RZ
RY + RZ
= 0.5 V
Because RZ is already known, RY can be expressed as follows:
RY
=
(0.5)(VM
(VUV )(I M
)
)
−
R
Z
(2)
Data Sheet
When RY and RZ are known, RX is calculated using the following
formula:
RX
=
(VM
(I M
)
)
−
R
Z
− RY
(3)
If VM, IM, VOV, or VUV change, each step must be recalculated.
Negative Voltage Monitoring Scheme
Figure 18 shows the circuit configuration for negative supply
voltage monitoring. To monitor a negative voltage, a 1 V reference
voltage is required to connect to the end node of the voltage
divider circuit. This reference voltage is generated internally
and is output through the REF pin.
REF ADM12914
RZ
VPH
VHx
OVx
RY 0.5V
VPL
VLx
RX
UVx
VM
Figure 18. Negative Undervoltage/Overvoltage Monitoring Configuration
The equations described previously in the Positive Voltage
Monitoring Scheme section need some minor modifications for
use with negative voltage monitoring. The 1 V reference voltage
is added to the overall voltage drop; it must therefore be sub-
tracted from VM, VUV, and VOV before using each in the previous
equations.
To monitor a negative voltage level, the resistor divider circuit
divides the voltage differential level between the 1 V reference
voltage and the negative supply voltage into high-side voltage,
VNH, and low-side voltage, VNL. Similar to the positive voltage
monitoring scheme, the high-side voltage, VNH, is connected to
the corresponding VHx pin and the low-side voltage, VNL, is
connected to the corresponding VLx pin. Refer to the Voltage
Monitoring Example section for further information.
THRESHOLD ACCURACY
The reset threshold accuracy is fundamental, especially at lower
voltage levels. Consider an FPGA application that requires a 1 V
core voltage input with a tolerance of ±5%, where the supply has
a specified regulation, for example, ±2.6%. As shown in Figure 19,
to ensure the supply is within the FPGA input voltage requirement
range, its voltage level must be monitored for UV and OV condi-
tions. The voltage swing on the supply itself causes the voltage
band available for setting the monitoring threshold to be quite
narrow. In this example, the threshold voltages, including the
Rev. E | Page 10 of 16
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