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PDF ADV3002 Data sheet ( Hoja de datos )
| Número de pieza | ADV3002 | |
| Descripción | 4:1 HDMI/DVI Switch | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
4:1 HDMI/DVI Switch with Equalization,
DDC/CEC Buffers and EDID Replication
ADV3002
FEATURES
4 inputs, 1 output HDMI/DVI links
±8 kV ESD protection on input pins
HDMI 1.4a receive and transmit compliant
Supports 250 Mbps to 2.25 Gbps data rates and beyond
Supports 25 MHz to 225 MHz pixel clocks and beyond
Fully buffered unidirectional inputs/outputs
Switchable 50 Ω on-chip input terminations with manual
or automatic control on channel switch
Equalized inputs with low added jitter compensate for
more than 20 meters of HDMI cable at 2.25 Gbps
Loss of signal (LOS) detect circuit on TMDS clock
Output disable feature for reduced power dissipation
Bidirectional DDC buffers (SDA and SCL)
EDID replication reduces component count, while enabling
simultaneous access to all HDMI sources
5 V combiner provides power to EDID replicator and CEC
buffer when local system power is off
Bidirectional buffered CEC line with integrated pull-up
resistors (26 kΩ)
Hot plug detect pulse low on channel switch with
programmable pulse width or direct manual control
Standards compatible: HDMI, DVI, HDCP, I2C
80-lead, 14 mm × 14 mm LQFP RoHS-compliant package
APPLICATIONS
Advanced television (HDTV) sets
Projectors
A/V receivers
Set-top boxes
GENERAL DESCRIPTION
The ADV3002 is a complete HDMI™/DVI link switch featuring
equalized transition minimized differential signaling (TMDS)
inputs, ideal for systems with long cable runs. The ADV3002
includes bidirectional buffering for the DDC bus and CEC line,
with integrated pull-up resistors for the CEC line. Additionally,
the ADV3002 includes an EDID replication function that enables
one EDID EEPROM to be shared for all four HDMI ports.
The ADV3002 is provided in a space-saving, 80-lead LQFP
surface-mount, Pb-free plastic package and is specified to
operate over the 0°C to 85°C temperature range.
I2C_SDA
I2C_SCL
I2C_ADDR[1:0]
AVCC
FUNCTIONAL BLOCK DIAGRAM
SEL[1:0] TX_EN
RESETB
SERIAL
PARALLEL
CONFIG
2 INTERFACE
CONTROL
LOGIC
ADV3002
AVCC
AVEE
AVCC
IN_x_CLK+
IN_x_CLK–
IN_x_DATA2+
IN_x_DATA2–
IN_x_DATA1+
IN_x_DATA1–
IN_x_DATA0+
IN_x_DATA0–
+
–
+
–
+
–
+
–
LOS
4
4
4
4
4
SWITCH
CORE
EQ
4
4
TMDS
+
–
OUT_CLK+
+
–
OUT_CLK–
OUT_DATA2+
+
–
+
–
OUT_DATA2–
OUT_DATA1+
OUT_DATA1–
OUT_DATA0+
OUT_DATA0–
AVCC
DDC_xxx_A
DDC_xxx_B
DDC_xxx_C
DDC_xxx_D
CEC_IN
P5V_A
P5V_B
P5V_C
P5V_D
HPD_A
HPD_B
HPD_C
HPD_D
2
2
2
2
SWITCH
CORE
3.3V
2
3.3V
DDC/CEC
BIDIRECTIONAL
EDID
REPLICATOR
CONTROL
2
5V
COMBINER
EDID EEPROM INTERFACE
HPD
CONTROL
AVCC
DDC_SCL_COM,
DDC_SDA_COM
CEC_OUT
EDID_ENABLE
EDID_SCL,
EDID_SDA
AMUXVCC
HOT PLUG DETECT
Figure 1.
PRODUCT HIGHLIGHTS
1. Input cable equalizer enables use of long cables at the input.
For a 24 AWG cable, the ADV3002 compensates for more
than 20 meters at data rates of up to 2.25 Gbps.
2. Auxiliary multiplexer isolates and buffers the DDC bus and
the CEC line, increasing total system capacitance limit.
3. EDID replication eliminates the need for multiple EDID
EEPROMs. EDID can be loaded from a single external
EEPROM or from a system microcontroller.
4. 5 V power combiner powers the EDID replicator and CEC
buffer when local system power is off.
5. Integrated hot plug detect pulse low on channel switch
with programmable pulse width or direct manual control.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevicesforitsuse,nor for anyinfringementsofpatentsor other
rightsof third partiesthat may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2008–2012 Analog Devices, Inc. All rights reserved.
1 page  
ADV3002
Data Sheet
Parameter
CEC CHANNEL
Input Capacitance, CAUX
Input Low Voltage, VIL
Input High Voltage, VIH
Output Low Voltage, VOL
Output High Voltage, VOH
Rise Time
Fall Time
Pull-Up Resistance
Leakage
HOT PLUG DETECT
Output Low Voltage, VOL
Test Conditions/Comments
Min
DC bias = 1.65 V, ac voltage = 2.5 V p-p, f = 100 kHz
IOL = 3 mA
10% to 90%, CLOAD = 1500 pF, RPULL-UP = 27 kΩ; or CLOAD = 7200 pF,
RPULL-UP = 3 kΩ
90% to 10%, CLOAD = 1500 pF, RPULL-UP = 27 kΩ; or CLOAD = 7200 pF,
RPULL-UP = 3 kΩ
2.0
2.5
Off-leakage test conditions1
RPU = 800 Ω
Typ Max Unit
5 15 pF
0.8 V
V
0.1 0.6 V
V
75 250 µs
0.2 50 µs
26 kΩ
1.8 µA
0.25 0.4 V
1 Off leakage test conditions are described in the HDMI Compliance Test Specification 1.3c Section 8, Test ID 8-14. To measure CEC leakage, connect the CEC line to
3.63 V via 26 kΩ ± 5 % resistor with an ammeter in series and with the power mains disabled.
POWER SUPPLY AND CONTROL LOGIC SPECIFICATIONS
Table 3.
Parameter
POWER SUPPLY
AVCC
P5V_x
AMUXVCC
QUIESCENT CURRENT
AVCC
P5V_x
AMUXVCC
POWER DISSIPATION
I2C® AND LOGIC INPUTS2
Input High Voltage, VIH
Input Low Voltage, VIL
I2C AND LOGIC OUTPUTS2
Output High Voltage, VOH
Output Low Voltage, VOL
Test Conditions/Comments
Operating range (3.3 V ± 10%)
Output voltage, total load1 = 50 mA
Outputs disabled
Outputs enabled
Main power on
Main power off
Main power on
Main power off
Outputs disabled
Outputs enabled
IOH = −2 mA
IOL = +2 mA
Min Typ
3.0 3.3
4.7 5
4.0 5
40
170
0.5
20
20
0.5
232
661
2.4
AVCC
Max Unit
3.6 V
5.5 V
5.5 V
60 mA
150 mA
10 mA
30 mA
30 mA
10 mA
381 mW
885 mW
V
1.0 V
V
0.4 V
1 The total load current includes current drawn by the ADV3002 as well as external devices powered from the AMUXVCC supply.
2 The ADV3002 I2C control and logic input pins are listed as Control in the Type column in Table 6. I2C pins are 5 V tolerant and based on the 3.3 V I2C bus specification.
Rev. B | Page 4 of 28
5 Page 
ADV3002
Data Sheet
TA = 27°C, AVCC = 3.3 V, AMUXVCC = 5.0 V, AVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 27 − 1, data rate = 2.25 Gbps,
TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted.
1.0
ALL CABLES = 24 AWG
0.9
0.8
0.7
1080p, 12-BIT
0.6 1080p, 10-BIT
1080p, 8-BIT
0.5 720p
3Gbps
0.4
0.3
0.2
0.1
0
0 10 20
INPUT CABLE LENGTH (m)
Figure 12. Jitter vs. Input Cable Length
30
100
90
80
70
60
50
40
30
20
10
0
0
DETERMINISTIC JITTER
RANDOM JITTER
10 20 30 40 50 60
TEMPERATURE (°C)
Figure 15. Jitter vs. Temperature
70
80
100
90
80
70
60
50
40
30
20
10
0
0
DETERMINISTIC JITTER
RANDOM JITTER
0.5 1.0 1.5 2.0 2.5 3.0 3.5
DATA RATE (Gbps)
1000
800
600
400
200
0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
DATA RATE (Gbps)
Figure 13. Jitter vs. Data Rate
Figure 16. Eye Height vs. Data Rate
100
90
80
70
60
50
40 DETERMINISTIC JITTER
30
20
10 RANDOM JITTER
0
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
SUPPLY VOLTAGE (V)
Figure 14. Jitter vs. Supply Voltage
1000
800
600
400
200
0
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
SUPPLY VOLTAGE (V)
Figure 17. Eye Height vs. Supply Voltage
Rev. B | Page 10 of 28
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet ADV3002.PDF ] | |
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