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PDF AD7193 Data sheet ( Hoja de datos )
| Número de pieza | AD7193 | |
| Descripción | 24-Bit Sigma-Delta ADC | |
| Fabricantes | Analog Devices | |
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Data Sheet
4-Channel, 4.8 kHz, Ultralow Noise,
24-Bit Sigma-Delta ADC with PGA
AD7193
FEATURES
Pressure measurement
Fast settling filter option
4 differential/8 pseudo differential input channels
RMS noise: 11 nV @ 4.7 Hz (gain = 128)
15.5 noise-free bits @ 2.4 kHz (gain = 128)
Up to 22 noise-free bits (gain = 1)
Temperature measurement
Flow measurement
Weigh scales
Chromatography
Medical and scientific instrumentation
Offset drift: ±5 nV/°C
Gain drift: ±1 ppm/°C
Specified drift over time
Automatic channel sequencer
Programmable gain (1 to 128)
Output data rate: 4.7 Hz to 4.8 kHz
Internal or external clock
GENERAL DESCRIPTION
The AD7193 is a low noise, complete analog front end for high
precision measurement applications. It contains a low noise,
24-bit sigma-delta (Σ-Δ) analog-to-digital converter (ADC).
The on-chip low noise gain stage means that signals of small
amplitude can interface directly to the ADC.
Simultaneous 50 Hz/60 Hz rejection
The device can be configured to have four differential inputs or
4 general-purpose digital outputs
eight pseudo differential inputs. The on-chip channel sequencer
Power supply
allows several channels to be enabled simultaneously, and the
AVDD: 3 V to 5.25 V
DVDD: 2.7 V to 5.25 V
Current: 4.65 mA
AD7193 sequentially converts on each enabled channel, simplifying
communication with the part. The on-chip 4.92 MHz clock can
be used as the clock source to the ADC or, alternatively, an external
Temperature range: −40°C to +105°C
clock or crystal can be used. The output data rate from the part
28-lead TSSOP and 32-lead LFCSP packages
can be varied from 4.7 Hz to 4.8 kHz.
Interface
3-wire serial
SPI, QSPI™, MICROWIRE™, and DSP compatible
Schmitt trigger on SCLK
The device has a very flexible digital filter, including a fast
settling option. Variables such as output data rate and settling
time are dependent on the option selected. The AD7193 also
includes a zero latency option.
APPLICATIONS
The part operates with a power supply from 3 V to 5.25 V. It
PLC/DCS analog input modules
consumes a current of 4.65 mA, and it is available in a 28-lead
Data acquisition
TSSOP package and a 32-lead LFCSP package.
Strain gage transducers
FUNCTIONAL BLOCK DIAGRAM
AVDD AGND DVDD DGND
REFIN1(+) REFIN1(–)
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AINCOM
BPDSW
AD7193
AGND
MUX
PGA
Σ-Δ
ADC
TEMP
SENSOR
CLOCK
CIRCUITRY
MCLK1 MCLK2
Figure 1.
SERIAL
INTERFACE
AND
CONTROL
LOGIC
DOUT/RDY
DIN
SCLK
CS
SYNC
P3
P2
P0/REFIN2(–) P1/REFIN2(+)
Rev. D
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2009–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD7193
Data Sheet
SPECIFICATIONS
AVDD = 3 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V; REFINx(+) = 2.5 V or AVDD, REFINx(−) = AGND,
MCLK = 4.92 MHz, TA = TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
ADC
Output Data Rate
No Missing Codes2
Resolution
RMS Noise and Output
Data Rates
Integral Nonlinearity
Gain = 12
Gain > 1
Offset Error4, 5
Min
4.7
1.17
1.56
24
24
Offset Error Drift vs.
Temperature
Offset Error Drift vs. Time
Gain Error4
Gain Drift vs.
Temperature
Gain Drift vs. Time
Power Supply Rejection
Common-Mode Rejection
@ DC
@ DC
@ 50 Hz, 60 Hz2
95
105
120
@ 50 Hz2
@ 60 Hz2
@ 50 Hz2
120
120
115
@ 60 Hz2
115
Typ Max
4800
1200
1600
±2
±2
±5
±15
±150/gain
±1
±0.5
±150/gain
±5
±5
25
±0.001
−0.39
±0.003
±0.005
±1
10
90
110
110
±10
±15
±30
±30
Unit Test Conditions/Comments1
Hz Chop disabled
Hz Chop enabled, sinc4 filter
Hz Chop enabled, sinc3 filter
Bits FS[9:0]3 > 1, sinc4 filter
Bits FS[9:0]3 > 4, sinc3 filter
See the RMS Noise and Resolution section
See the RMS Noise and Resolution section
ppm of FSR
ppm of FSR
ppm of FSR
ppm of FSR
µV
µV
µV
nV/°C
AVDD = 5 V
AVDD = 3 V
AVDD = 5 V
AVDD = 3 V
Chop disabled
Chop enabled, AVDD = 5 V
Chop enabled, AVDD = 3 V
Gain = 1 to 16; chop disabled
nV/°C
nV/°C
nV/1000
hours
%
%
%
%
ppm/°C
Gain = 32 to 128; chop disabled
Chop enabled
Gain > 32
AVDD = 5 V, gain = 1, TA = 25°C
(factory calibration conditions)
Gain = 128, before full-scale calibration
(see Table 27)
Gain > 1, after internal full-scale calibration,
AVDD ≥ 4.75 V
Gain > 1, after internal full-scale calibration,
AVDD < 4.75 V
ppm/
1000 hours
dB
dB
Gain = 1
Gain = 1, VIN = 1 V
Gain > 1, VIN = 1 V/gain
dB Gain = 1, VIN = 1 V
dB Gain > 1, VIN = 1 V/gain
dB 10 Hz output data rate, 50 Hz ± 1 Hz,
60 Hz ± 1 Hz
dB 50 Hz output data rate, 50 Hz ± 1 Hz
dB 60 Hz output data rate, 60 Hz ± 1 Hz
dB Fast settling, FS[9:0]3 = 6, average by 16,
50 Hz ± 1 Hz
dB Fast settling, FS[9:0]3 = 5, average by 16,
60 Hz ± 1 Hz
Rev. D | Page 4 of 56
5 Page 
AD7193
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
AVDD to AGND
DVDD to AGND
AGND to DGND
Analog Input Voltage to AGND
Reference Input Voltage to AGND
Digital Input Voltage to DGND
Digital Output Voltage to DGND
AINx/Digital Input Current
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
Lead Temperature, Soldering Reflow
Rating
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−0.3 V to +0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
10 mA
−40°C to +105°C
−65°C to +150°C
150°C
260°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Data Sheet
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for the surface-mount packages.
Table 4. Thermal Resistance
Package Type
θJA
28-Lead TSSOP
97.9
32-Lead LFCSP
32.5
θJC
14
32.71
Unit
°C/W
°C/W
ESD CAUTION
Rev. D | Page 10 of 56
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD7193.PDF ] | |
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