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PDF AD8120 Data sheet ( Hoja de datos )
| Número de pieza | AD8120 | |
| Descripción | Triple Skew-Compensating Video Delay Line | |
| Fabricantes | Analog Devices | |
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Data Sheet
Triple Skew-Compensating Video Delay
Line with Analog and Digital Control
AD8120
FEATURES
Corrects for unshielded twisted pair (UTP) cable skew
Delay of up to 50 ns per channel
High speed
200 MHz BW @ VOUT = 1.4 V p-p and 0 ns delay
150 MHz BW @ VOUT = 1.4 V p-p and 50 ns delay
Excellent channel-to-channel matching
30 mV offset matching RTI
0.8% gain matching
Low output offset
±30 mV RTI
No external circuitry required to correct for offsets
Independent red, green, and blue delay controls
Drives 4 double-terminated video loads
Digital and analog delay control
6-bit SPI bus
I2C bus
Analog voltage control
Fixed gain of 2
Low noise
High differential input impedance: 500 kΩ
32-lead, 5 mm × 5 mm LFCSP
APPLICATIONS
Keyboard-video-mouse (KVM)
Digital signage
RGB video over UTP cable
Professional video projection and distribution
HD video
Security video
General broadband delay lines
GENERAL DESCRIPTION
The AD8120 is a triple broadband skew-compensating delay line
that corrects for time mismatch between video signals incurred
by transmission in unshielded twisted pairs of Category 5 and
Category 6 type cables. Skew between the individual pairs exists
in most types of multipair UTP cables due to the different twist
rates that are used for each pair to minimize crosstalk between
pairs. For this reason, some pairs are longer than others, and in
long cables, the difference in propagation time between two pairs
can be well into the tens of nanoseconds.
The AD8120 contains three delay paths that provide broadband
delays up to 50 ns, in 0.8 ns increments, using 64 digital control
steps or analog control adjustment. The delay technique used in
the AD8120 minimizes noise and offset at the outputs.
The bandwidth of the AD8120 ranges from 150 MHz to 200 MHz,
depending on the delay setting. This wide bandwidth makes the
AD8120 ideal for use in applications that receive high resolution
video over UTP cables.
The logic circuitry of the AD8120 provides individual delay con-
trols for each channel. The delay times are set independently
using a standard 4-wire SPI bus or a standard I2C bus, or by
applying analog control voltages to the VCR, VCG, and VCB pins.
Analog control offers a simple solution for systems that do not
have digital control available.
The AD8120 is designed to be used with the AD8123 triple
UTP equalizer in video over UTP applications, but it can
also be used in other applications where similar controllable
broadband delays are required.
The AD8120 is available in a 5 mm × 5 mm, 32-lead LFCSP
and is rated to operate over the industrial temperature range
of −40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
Rd
Gd
Bd
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2009–2012 Analog Devices, Inc. All rights reserved.
1 page  
AD8120
Data Sheet
Parameter
Test Conditions/Comments
Min Typ Max Unit
DIGITAL CONTROL INPUT CHARACTERISTICS SDO/SDA, SCK/SCL, SDI/A1, CS/A0, SER_SEL,
(SEE BELOW FOR POWER DOWN)
MODE
Input Bias Current
2 μA
Input High Voltage
2.6 V
Input Low Voltage
0.6 V
Output High Voltage
4.5 V
Output Low Voltage
0.6 V
POWER DOWN CHARACTERISTICS
PD
Input High Voltage
4.0 V
Input Low Voltage
0.6 V
SPI TIMING CHARACTERISTICS
Clock Frequency
SCK
10 MHz
CS Setup Time, t1
CS to SCK
5 ns
Clock Pulse High, t2
Clock Pulse Low, t3
Data Setup Time, t4
Data Hold Time, t5
SCK
SCK
SDI to SCK
SDI to SCK
50 ns
50 ns
5 ns
5 ns
CS Hold Time, t6
SCK to CS
5 ns
I2C TIMING CHARACTERISTICS
Clock Frequency
SCL
100 kHz
Start Setup Time, t1
Clock Pulse High, t2
SDA to SCL
SCL
10 ns
5 μs
Clock Pulse Low, t3
SCL
5 μs
Data Setup Time, t4
SDA (input) to SCL
100
ns
Data Hold Time, t5
Hold Time, t6
SDA (input) to SCL
SCL to SDA
100
10
ns
ns
POWER SUPPLY
Positive Supply Range
4.5 5.5 V
Negative Supply Range
−5.5 −4.5 V
Positive Quiescent Current
Delay = 0 ns
44 mA
Delay = 50 ns
114 mA
Powered down, PD low
4 mA
Negative Quiescent Current
Delay = 0 ns
37 mA
Delay = 50 ns
108 mA
Powered down, PD low
0.5 mA
Quiescent Current Drift
TMIN to TMAX, delay = 0 ns
0.13 mA/°C
TMIN to TMAX, delay = 50 ns
0.36 mA/°C
+PSRR
RL = 150 Ω, delay = 50 ns
56 dB
−PSRR
RL = 150 Ω, delay = 50 ns
44 dB
Rev. A | Page 4 of 16
5 Page 
AD8120
ANALOG CONTROL
A number of video transmission systems do not have a microcon-
troller embedded or otherwise available to provide digital control.
These systems require analog control. Potentiometer control is
one of the most common ways to implement analog control (see
Figure 25). To select analog control, set the MODE pin high.
The AD8120 has one analog control input for each channel: VCR,
VCG, and VCB. The maximum recommended control voltage range
on these inputs is 0 V to 2.0 V, although the actual control range
where delay changes take effect is smaller and lies within this larger
range. An internal ADC converts the analog control voltages
into binary delay codes; therefore, the analog control is discrete
with nominally 0.8 ns resolution. Figure 6 illustrates the typical
transfer characteristic between control voltage and delay code.
POWER DOWN
The power-down feature is intended to be used to reduce power
consumption when a particular device is not in use and does
not place the output in a high-Z state when asserted. Note that
the input high level for the power-down input is higher than it
is for the other digital inputs. Refer to the Specifications in
Table 1 for details.
DIGITAL CONTROL
Set the MODE pin low to select digital control (SPI or I2C). Set
the SER_SEL pin high to select SPI mode, or set the SER_SEL
pin low to select I2C mode. Table 6 provides the bit values for
reading and writing the red, green, and blue registers.
Table 6. Read/Write Instruction and Color Registers
Operation
R/W Bit
C1 Bit
C0 Bit
Write Red
0
0
0
Read Red
1
0
0
Write Green
0
0
1
Read Green
1
0
1
Write Blue
0
1
0
Read Blue
1
1
0
Data Sheet
SPI Control
The SPI bus operates in full-duplex mode and consists of four
digital lines: SDI, SDO, SCK, and CS.
Table 7. AD8120 SPI Pin Descriptions
Pin
Pin No. Name Description
29 SDI Serial data input, master out slave in (MOSI)
2 SDO Serial data output, master in slave out (MISO)
30 SCK Serial clock from master
31 CS Chip select; active low
The AD8120 is programmed in SPI mode using a 2-byte sequence
(see Table 8). Data is clocked into the SDI pin or clocked out of
the SDO pin on the rising edge of the clock, MSB first. The first
byte contains the read/write (R/W) instruction and the color reg-
ister address (see Table 6). The second byte contains the delay
code to write to the part (R/W = 0) or the stored delay code to
read from the part (R/W = 1).
Figure 17 shows how to write Delay Code 42 to the green
register. Figure 18 shows how to read Delay Code 21 from
the blue register.
Table 8. SPI 2-Byte Sequence
Byte 1 (R/W Bit and Color Register)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
SDI R/W 0 0 0 0 0 C1
SDO X X X X X X X
Bit 0
C0
X
Bit 7
X
X
Bit 6
X
X
Bit 5
D5
D5
Byte 2 (Data)
Bit 4 Bit 3
D4 D3
D4 D3
Bit 2
D2
D2
Bit 1
D1
D1
Bit 0
D0
D0
Rev. A | Page 10 of 16
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet AD8120.PDF ] | |
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