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PDF 26DF081A Data sheet ( Hoja de datos )
| Número de pieza | 26DF081A | |
| Descripción | AT26DF081A | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Single 2.7V - 3.6V Supply
• Serial Peripheral Interface (SPI) Compatible
– Supports SPI Modes 0 and 3
• 70 MHz Maximum Clock Frequency
• Flexible, Uniform Erase Architecture
– 4-Kbyte Blocks
– 32-Kbyte Blocks
– 64-Kbyte Blocks
– Full Chip Erase
• Optimized Physical Sectoring for Code Shadowing and Code + Data Storage
Applications
– One 32-Kbyte Top Boot Sector
– Two 8-Kbyte Sectors
– One 16-Kbyte Sector
– Fifteen 64-Kbyte Sectors
• Individual Sector Protection for Program/Erase Protection
• Hardware Controlled Locking of Protected Sectors
• Flexible Programming Options
– Byte/Page Program (1 to 256 Bytes)
– Sequential Program Mode Capability
• JEDEC Standard Manufacturer and Device ID Read Methodology
• Low Power Dissipation
– 7 mA Active Read Current (Typical)
– 11 µA Deep Power-down Current (Typical)
• Endurance: 100,000 Program/Erase Cycles
• Data Retention: 20 Years
• Complies with Full Industrial Temperature Range
• Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
– 8-lead SOIC (150-mil and 200-mil wide)
ww1w..DataDSheeset4cUr.ciopmtion
The AT26DF081A is a serial interface Flash memory device designed for use in a
wide variety of high-volume consumer-based applications in which program code is
shadowed from Flash memory into embedded or external RAM for execution. The
flexible erase architecture of the AT26DF081A, with its erase granularity as small as
4 Kbytes, makes it ideal for data storage as well, eliminating the need for additional
data storage EEPROM devices.
The physical sectoring and the erase block sizes of the AT26DF081A have been opti-
mized to meet the needs of today’s code and data storage applications. By optimizing
the size of the physical sectors and erase blocks, the memory space can be used
much more efficiently. Because certain code modules and data storage segments
must reside by themselves in their own protected sectors, the wasted and unused
memory space that occurs with large sectored and large block erase Flash memory
devices can be greatly reduced. This increased memory space efficiency allows addi-
tional code routines and data storage segments to be added while still maintaining the
same overall device density.
8-megabit
2.7-volt Only
Serial Firmware
DataFlash®
Memory
AT26DF081A
Preliminary
3600A–DFLASH–11/05
1 page  
AT26DF081A [Preliminary]
5. Device Operation
The AT26DF081A is controlled by a set of instructions that are sent from a host controller, com-
monly referred to as the SPI Master. The SPI Master communicates with the AT26DF081A via
the SPI bus which is comprised of four signal lines: Chip Select (CS), Serial Clock (SCK), Serial
Input (SI), and Serial Output (SO).
The SPI protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode
differing in respect to the SCK polarity and phase and how the polarity and phase control the
flow of data on the SPI bus. The AT26DF081A supports the two most common modes, SPI
modes 0 and 3. The only difference between SPI modes 0 and 3 is the polarity of the SCK signal
when in the inactive state (when the SPI Master is in standby mode and not transferring any
data). With SPI modes 0 and 3, data is always latched in on the rising edge of SCK and always
output on the falling edge of SCK.
Figure 5-1. SPI Mode 0 and 3
CS
SCK
SI MSB
LSB
SO
MSB
LSB
6. Commands and Addressing
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A valid instruction or operation must always be started by first asserting the CS pin. After the CS
pin has been asserted, the SPI Master must then clock out a valid 8-bit opcode on the SPI bus.
Following the opcode, instruction dependent information such as address and data bytes would
then be clocked out by the SPI Master. All opcode, address, and data bytes are transferred with
the most significant bit (MSB) first. An operation is ended by deasserting the CS pin.
Opcodes not supported by the AT26DF081A will be ignored by the device and no operation will
be started. The device will continue to ignore any data presented on the SI pin until the start of
the next operation (CS pin being deasserted and then reasserted). In addition, if the CS pin is
deasserted before complete opcode and address information is sent to the device, then no oper-
ation will be performed and the device will simply return to the idle state and wait for the next
operation.
Addressing of the device requires a total of three bytes of information to be sent, representing
address bits A23 - A0. Since the upper address limit of the AT26DF081A memory array is
0FFFFFh, address bits A23 - A20 are always ignored by the device.
3600A–DFLASH–11/05
5
5 Page 
AT26DF081A [Preliminary]
Figure 8-3. Sequential Program Mode – Status Register Polling
CS
Seqeuntial Program Mode
Command
Status Register Read Seqeuntial Program Mode
Command
Command
SI Opcode A23-16 A15-8 A7-0 Data
05h
Opcode Data
SO
First Address to Program
HIGH-IMPEDANCE
STATUS REGISTER
DATA
Seqeuntial Program Mode Write Disable
Command
Command
05h Opcode Data 04h 05h
STATUS REGISTER
DATA
STATUS REGISTER
DATA
Note: Each transition
shown for SI represents one byte (8 bits)
Figure 8-4. Sequential Program Mode – Waiting Maximum Byte Program Time
CS
Seqeuntial Program Mode
Command
tBP
Seqeuntial Program Mode
Command
tBP
Seqeuntial Program Mode
Command
SI Opcode A23-16 A15-8 A7-0 Data
Opcode Data
Opcode Data
First Address to Program
SO HIGH-IMPEDANCE
tBP
Write Disable
Command
04h
Note: Each transition
shown for SI represents one byte (8 bits)
8.3 Block Erase
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A block of 4, 32, or 64 Kbytes can be erased (all bits set to the logical “1” state) in a single oper-
ation by using one of three different opcodes for the Block Erase command. An opcode of 20h is
used for a 4-Kbyte erase, an opcode of 52h is used for a 32-Kbyte erase, and an opcode of D8h
is used for a 64-Kbyte erase. Before a Block Erase command can be started, the Write Enable
command must have been previously issued to the device to set the WEL bit of the Status Reg-
ister to a logical “1” state.
To perform a Block Erase, the CS pin must first be asserted and the appropriate opcode (20h,
52h or D8h) must be clocked into the device. After the opcode has been clocked in, the three
address bytes specifying an address within the 4-, 32-, or 64-Kbyte block to be erased must be
clocked in. Any additional data clocked into the device will be ignored. When the CS pin is deas-
serted, the device will erase the appropriate block. The erasing of the block is internally self-
timed and should take place in a time of tBLKE.
Since the Block Erase command erases a region of bytes, the lower order address bits do not
need to be decoded by the device. Therefore, for a 4-Kbyte erase, address bits A11 - A0 will be
ignored by the device and their values can be either a logical “1” or “0”. For a 32-Kbyte erase,
address bits A14 - A0 will be ignored, and for a 64-Kbyte erase, address bits A15 - A0 will be
ignored by the device. Despite the lower order address bits not being decoded by the device, the
complete three address bytes must still be clocked into the device before the CS pin is deas-
serted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits);
otherwise, the device will abort the operation and no erase operation will be performed.
3600A–DFLASH–11/05
11
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